Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
09/352449 NONVOLATILE MEMORY DEVICE AND FABRICATION METHOD THEREOF Jul 12, 1999 Abandoned
Array ( [id] => 1553488 [patent_doc_number] => 06348378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method of making a non-volatile semiconductor device with reduced program disturbance' [patent_app_type] => B1 [patent_app_number] => 09/349728 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6576 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 505 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348378.pdf [firstpage_image] =>[orig_patent_app_number] => 09349728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349728
Method of making a non-volatile semiconductor device with reduced program disturbance Jul 7, 1999 Issued
Array ( [id] => 1509263 [patent_doc_number] => 06441415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity' [patent_app_type] => B1 [patent_app_number] => 09/344580 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2815 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441415.pdf [firstpage_image] =>[orig_patent_app_number] => 09344580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344580
Ferroelectric and paraelectric thin film devices using dopants which eliminate ferroelectricity Jun 24, 1999 Issued
Array ( [id] => 6593877 [patent_doc_number] => 20020063276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'METHOD OF FORMING A FLOATING GATE MEMORY CELL STRUCTURE' [patent_app_type] => new [patent_app_number] => 09/332109 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5709 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20020063276.pdf [firstpage_image] =>[orig_patent_app_number] => 09332109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332109
Method of forming a floating gate memory cell structure Jun 13, 1999 Issued
Array ( [id] => 1419028 [patent_doc_number] => 06506643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method for forming a damascene FeRAM cell structure' [patent_app_type] => B1 [patent_app_number] => 09/330900 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4546 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506643.pdf [firstpage_image] =>[orig_patent_app_number] => 09330900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330900
Method for forming a damascene FeRAM cell structure Jun 10, 1999 Issued
Array ( [id] => 4275541 [patent_doc_number] => 06281088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of manufacturing SRAM having enhanced cell ratio' [patent_app_type] => 1 [patent_app_number] => 9/324289 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281088.pdf [firstpage_image] =>[orig_patent_app_number] => 324289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324289
Method of manufacturing SRAM having enhanced cell ratio Jun 1, 1999 Issued
Array ( [id] => 1448010 [patent_doc_number] => 06369406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method for localizing point defects causing leakage currents in a non-volatile memory device' [patent_app_type] => B1 [patent_app_number] => 09/311258 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2790 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369406.pdf [firstpage_image] =>[orig_patent_app_number] => 09311258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311258
Method for localizing point defects causing leakage currents in a non-volatile memory device May 12, 1999 Issued
Array ( [id] => 1568474 [patent_doc_number] => 06376912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Common mode choke coil of the conductor/insulator stacked type that uses a high machinability substrate and benzocyclobutene as the insulator' [patent_app_type] => B1 [patent_app_number] => 09/298437 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4090 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376912.pdf [firstpage_image] =>[orig_patent_app_number] => 09298437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298437
Common mode choke coil of the conductor/insulator stacked type that uses a high machinability substrate and benzocyclobutene as the insulator Apr 22, 1999 Issued
Array ( [id] => 4366096 [patent_doc_number] => 06255690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/282204 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7357 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255690.pdf [firstpage_image] =>[orig_patent_app_number] => 282204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282204
Non-volatile semiconductor memory device Mar 30, 1999 Issued
Array ( [id] => 4413903 [patent_doc_number] => 06265729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method for detecting and characterizing plasma-etch induced damage in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/277338 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3685 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265729.pdf [firstpage_image] =>[orig_patent_app_number] => 277338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277338
Method for detecting and characterizing plasma-etch induced damage in an integrated circuit Mar 25, 1999 Issued
Array ( [id] => 4094636 [patent_doc_number] => 06133600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Memory device with improved domed capacitors' [patent_app_type] => 1 [patent_app_number] => 9/256868 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3273 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133600.pdf [firstpage_image] =>[orig_patent_app_number] => 256868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256868
Memory device with improved domed capacitors Feb 23, 1999 Issued
Array ( [id] => 1544387 [patent_doc_number] => 06373138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Integrated circuit with conductive lines disposed within isolation regions' [patent_app_type] => B1 [patent_app_number] => 09/249288 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4915 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373138.pdf [firstpage_image] =>[orig_patent_app_number] => 09249288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249288
Integrated circuit with conductive lines disposed within isolation regions Feb 9, 1999 Issued
Array ( [id] => 1424217 [patent_doc_number] => 06515328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor devices with reduced control gate dimensions' [patent_app_type] => B1 [patent_app_number] => 09/244429 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4111 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515328.pdf [firstpage_image] =>[orig_patent_app_number] => 09244429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244429
Semiconductor devices with reduced control gate dimensions Feb 3, 1999 Issued
Array ( [id] => 4224477 [patent_doc_number] => 06040594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'High permittivity ST thin film and a capacitor for a semiconductor integrated circuit having such a thin film' [patent_app_type] => 1 [patent_app_number] => 9/205398 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2245 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040594.pdf [firstpage_image] =>[orig_patent_app_number] => 205398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205398
High permittivity ST thin film and a capacitor for a semiconductor integrated circuit having such a thin film Dec 3, 1998 Issued
Array ( [id] => 6879058 [patent_doc_number] => 20010030343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS' [patent_app_type] => new [patent_app_number] => 09/203149 [patent_app_country] => US [patent_app_date] => 1998-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20010030343.pdf [firstpage_image] =>[orig_patent_app_number] => 09203149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203149
EEPROM cell with tunneling across entire separated channels Nov 30, 1998 Issued
Array ( [id] => 6221829 [patent_doc_number] => 20020003244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'LOW POWER RAM MEMORY CELL USING A PRECHARGE LINE PULSE DURING WRITE OPERATION' [patent_app_type] => new [patent_app_number] => 09/200079 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3078 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003244.pdf [firstpage_image] =>[orig_patent_app_number] => 09200079 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200079
Low power RAM memory cell using a precharge line pulse during write operation Nov 24, 1998 Issued
Array ( [id] => 1422266 [patent_doc_number] => 06518620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'EEPROM memory cell with increased dielectric integrity' [patent_app_type] => B2 [patent_app_number] => 09/195089 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6173 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518620.pdf [firstpage_image] =>[orig_patent_app_number] => 09195089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195089
EEPROM memory cell with increased dielectric integrity Nov 17, 1998 Issued
Array ( [id] => 538967 [patent_doc_number] => 07173317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Electrical and thermal contact for use in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 09/189098 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4532 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173317.pdf [firstpage_image] =>[orig_patent_app_number] => 09189098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189098
Electrical and thermal contact for use in semiconductor devices Nov 8, 1998 Issued
Array ( [id] => 6137756 [patent_doc_number] => 20020000588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR WITH TENSILE STRESS PROPERTIES' [patent_app_type] => new [patent_app_number] => 09/177038 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2318 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000588.pdf [firstpage_image] =>[orig_patent_app_number] => 09177038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177038
SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR WITH TENSILE STRESS PROPERTIES Oct 21, 1998 Abandoned
Array ( [id] => 4380675 [patent_doc_number] => 06277671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Methods of forming integrated circuit packages' [patent_app_type] => 1 [patent_app_number] => 9/176479 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3646 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277671.pdf [firstpage_image] =>[orig_patent_app_number] => 176479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176479
Methods of forming integrated circuit packages Oct 19, 1998 Issued
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