Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
09/160778 FERROELECTRIC THIN FILMS OF REDUCED TETRAGONALITY Sep 23, 1998 Abandoned
Array ( [id] => 4347406 [patent_doc_number] => 06214647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method for bonding heatsink to multiple-height chip' [patent_app_type] => 1 [patent_app_number] => 9/159239 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214647.pdf [firstpage_image] =>[orig_patent_app_number] => 159239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159239
Method for bonding heatsink to multiple-height chip Sep 22, 1998 Issued
09/143089 METHODS AND ARRANGEMENTS FOR NITROGEN-RICH REGIONS IN NON-VOLTILE SEMICONDUCTOR MEMORY DEVICES Aug 27, 1998 Abandoned
Array ( [id] => 4303761 [patent_doc_number] => 06326266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix' [patent_app_type] => 1 [patent_app_number] => 9/141849 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3815 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326266.pdf [firstpage_image] =>[orig_patent_app_number] => 141849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141849
Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix Aug 26, 1998 Issued
Array ( [id] => 4351161 [patent_doc_number] => 06285076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Press-connection semiconductor device and press-connection semiconductor assembly' [patent_app_type] => 1 [patent_app_number] => 9/140538 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3588 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285076.pdf [firstpage_image] =>[orig_patent_app_number] => 140538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140538
Press-connection semiconductor device and press-connection semiconductor assembly Aug 25, 1998 Issued
Array ( [id] => 6947942 [patent_doc_number] => 20010021577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'METHOD FOR FORMING SIDEWALL SPACERS USING FREQUENCY DOUBLING HYBRID RESIST AND DEVICE FORMED THEREBY' [patent_app_type] => new [patent_app_number] => 09/141009 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9327 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021577.pdf [firstpage_image] =>[orig_patent_app_number] => 09141009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141009
METHOD FOR FORMING SIDEWALL SPACERS USING FREQUENCY DOUBLING HYBRID RESIST AND DEVICE FORMED THEREBY Aug 25, 1998 Abandoned
Array ( [id] => 1417575 [patent_doc_number] => 06528894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Use of nitrides for flip-chip encapsulation' [patent_app_type] => B1 [patent_app_number] => 09/138038 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4676 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528894.pdf [firstpage_image] =>[orig_patent_app_number] => 09138038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138038
Use of nitrides for flip-chip encapsulation Aug 19, 1998 Issued
Array ( [id] => 4309474 [patent_doc_number] => 06188102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Non-volatile semiconductor memory device having multiple different sized floating gates' [patent_app_type] => 1 [patent_app_number] => 9/127687 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 56 [patent_no_of_words] => 5807 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188102.pdf [firstpage_image] =>[orig_patent_app_number] => 127687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/127687
Non-volatile semiconductor memory device having multiple different sized floating gates Jul 30, 1998 Issued
Array ( [id] => 6885905 [patent_doc_number] => 20010019174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'METHOD AND APPARATUS FOR ASSEMBLING A CONFORMAL CHIP CARRIER TO A FLIP CHIP' [patent_app_type] => new [patent_app_number] => 09/116368 [patent_app_country] => US [patent_app_date] => 1998-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4375 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019174.pdf [firstpage_image] =>[orig_patent_app_number] => 09116368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116368
Fixture for attaching a conformal chip carrier to a flip chip Jul 15, 1998 Issued
Array ( [id] => 4294428 [patent_doc_number] => 06211573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor' [patent_app_type] => 1 [patent_app_number] => 9/096498 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 31810 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211573.pdf [firstpage_image] =>[orig_patent_app_number] => 096498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096498
Semiconductor device with an improved lead-chip adhesion structure and lead frame to be used therefor Jun 11, 1998 Issued
Array ( [id] => 1603260 [patent_doc_number] => 06433440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Semiconductor device having a porous buffer layer for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/092138 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 7383 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433440.pdf [firstpage_image] =>[orig_patent_app_number] => 09092138 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092138
Semiconductor device having a porous buffer layer for semiconductor device Jun 4, 1998 Issued
Array ( [id] => 3967067 [patent_doc_number] => 05956593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Semiconductor device comprising an MOS capacitance' [patent_app_type] => 1 [patent_app_number] => 9/084384 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 2973 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956593.pdf [firstpage_image] =>[orig_patent_app_number] => 084384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084384
Semiconductor device comprising an MOS capacitance May 26, 1998 Issued
09/083628 METHOD AND APPARATUS FOR OPERATING FLASH MEMORY CELLS May 21, 1998 Abandoned
Array ( [id] => 7117928 [patent_doc_number] => 20010001492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE STRUCTURE WITH SUPERIMPOSED BIT LINES AND SHORT-CIRCUIT METAL STRIPS' [patent_app_type] => new-utility [patent_app_number] => 09/081881 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3357 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001492.pdf [firstpage_image] =>[orig_patent_app_number] => 09081881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/081881
Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips May 18, 1998 Issued
Array ( [id] => 1440991 [patent_doc_number] => 06335238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Integrated dielectric and method' [patent_app_type] => B1 [patent_app_number] => 09/073087 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3920 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335238.pdf [firstpage_image] =>[orig_patent_app_number] => 09073087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073087
Integrated dielectric and method May 4, 1998 Issued
Array ( [id] => 4258806 [patent_doc_number] => 06258663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for forming storage node' [patent_app_type] => 1 [patent_app_number] => 9/071309 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258663.pdf [firstpage_image] =>[orig_patent_app_number] => 071309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071309
Method for forming storage node Apr 30, 1998 Issued
Array ( [id] => 4337204 [patent_doc_number] => 06313536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Semicoductor device having a multilayered interconnection structure' [patent_app_type] => 1 [patent_app_number] => 9/056849 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 7792 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313536.pdf [firstpage_image] =>[orig_patent_app_number] => 056849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056849
Semicoductor device having a multilayered interconnection structure Apr 7, 1998 Issued
Array ( [id] => 4355117 [patent_doc_number] => 06215145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Dense SOI flash memory array structure' [patent_app_type] => 1 [patent_app_number] => 9/055347 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4728 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215145.pdf [firstpage_image] =>[orig_patent_app_number] => 055347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055347
Dense SOI flash memory array structure Apr 5, 1998 Issued
Array ( [id] => 1421261 [patent_doc_number] => 06509606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process' [patent_app_type] => B1 [patent_app_number] => 09/053199 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4710 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509606.pdf [firstpage_image] =>[orig_patent_app_number] => 09053199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053199
Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process Mar 31, 1998 Issued
Array ( [id] => 1587745 [patent_doc_number] => 06359295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-19 [patent_title] => 'Ferroelectric memory devices including patterned conductive layers' [patent_app_type] => B2 [patent_app_number] => 09/052718 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3850 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359295.pdf [firstpage_image] =>[orig_patent_app_number] => 09052718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052718
Ferroelectric memory devices including patterned conductive layers Mar 30, 1998 Issued
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