Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 4350850
[patent_doc_number] => 06285054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-04
[patent_title] => 'Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings'
[patent_app_type] => 1
[patent_app_number] => 9/052057
[patent_app_country] => US
[patent_app_date] => 1998-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/052057 | Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings | Mar 29, 1998 | Issued |
09/047438 | COPPER METALIZATION WITH IMPROVED ELECTROMIGRATION RESISTANCE | Mar 24, 1998 | Abandoned |
Array
(
[id] => 4389975
[patent_doc_number] => 06262469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/047237
[patent_app_country] => US
[patent_app_date] => 1998-03-25
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[firstpage_image] =>[orig_patent_app_number] => 047237
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/047237 | Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor | Mar 24, 1998 | Issued |
Array
(
[id] => 4257298
[patent_doc_number] => 06207991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same'
[patent_app_type] => 1
[patent_app_number] => 9/045269
[patent_app_country] => US
[patent_app_date] => 1998-03-20
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 045269
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/045269 | Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same | Mar 19, 1998 | Issued |
Array
(
[id] => 4302547
[patent_doc_number] => 06187634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Process for making an EEPROM active area castling'
[patent_app_type] => 1
[patent_app_number] => 9/045737
[patent_app_country] => US
[patent_app_date] => 1998-03-19
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[firstpage_image] =>[orig_patent_app_number] => 045737
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Array
(
[id] => 4380574
[patent_doc_number] => 06261867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Method of making a package for microelectronic devices using iron oxide as a bonding agent'
[patent_app_type] => 1
[patent_app_number] => 9/039058
[patent_app_country] => US
[patent_app_date] => 1998-03-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/039058 | Method of making a package for microelectronic devices using iron oxide as a bonding agent | Mar 12, 1998 | Issued |
09/037849 | DUAL DIAMETER CONTACT PLUG AND METHOD OF MAKING | Mar 9, 1998 | Abandoned |
Array
(
[id] => 4185633
[patent_doc_number] => 06093606
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Method of manufacture of vertical stacked gate flash memory device'
[patent_app_type] => 1
[patent_app_number] => 9/035049
[patent_app_country] => US
[patent_app_date] => 1998-03-05
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[firstpage_image] =>[orig_patent_app_number] => 035049
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/035049 | Method of manufacture of vertical stacked gate flash memory device | Mar 4, 1998 | Issued |
09/034338 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN INTERLAYER INSULATING FILM FORMED UNDER A BONDING PAD AND ARRANGED TO PREVENT PEELING OF THE BONDING PAD | Mar 3, 1998 | Abandoned |
09/026539 | NONVOLATILE MEMORY DEVICES INCLUDING BIRD'S BEAK OXIDE AND METHODS FOR FABRICATING THE SAME | Feb 18, 1998 | Abandoned |
Array
(
[id] => 4277633
[patent_doc_number] => 06323510
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45.degree. angles'
[patent_app_type] => 1
[patent_app_number] => 9/023819
[patent_app_country] => US
[patent_app_date] => 1998-02-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/323/06323510.pdf
[firstpage_image] =>[orig_patent_app_number] => 023819
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023819 | Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45.degree. angles | Feb 12, 1998 | Issued |
Array
(
[id] => 4222784
[patent_doc_number] => 06087700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Gate having a barrier of titanium silicide'
[patent_app_type] => 1
[patent_app_number] => 9/021729
[patent_app_country] => US
[patent_app_date] => 1998-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 021729
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/021729 | Gate having a barrier of titanium silicide | Feb 10, 1998 | Issued |
Array
(
[id] => 1107666
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[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-26
[patent_title] => 'Method for forming isolation in flash memory wafer'
[patent_app_type] => B1
[patent_app_number] => 09/019409
[patent_app_country] => US
[patent_app_date] => 1998-02-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/019409 | Method for forming isolation in flash memory wafer | Feb 4, 1998 | Issued |
Array
(
[id] => 4387036
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Non-linear optical device using quantum dots'
[patent_app_type] => 1
[patent_app_number] => 9/018858
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 018858
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/018858 | Non-linear optical device using quantum dots | Feb 3, 1998 | Issued |
Array
(
[id] => 4163513
[patent_doc_number] => 06114760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Ball grid array (BGA) semiconductor package member'
[patent_app_type] => 1
[patent_app_number] => 9/010149
[patent_app_country] => US
[patent_app_date] => 1998-01-21
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[firstpage_image] =>[orig_patent_app_number] => 010149
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010149 | Ball grid array (BGA) semiconductor package member | Jan 20, 1998 | Issued |
Array
(
[id] => 4162640
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
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[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/008627 | Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays | Jan 15, 1998 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Leadframe finger support'
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[firstpage_image] =>[orig_patent_app_number] => 006237
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/006237 | Leadframe finger support | Jan 12, 1998 | Issued |
Array
(
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Semiconductor device having a monotonically decreasing impurity concentration'
[patent_app_type] => 1
[patent_app_number] => 9/003359
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[patent_app_date] => 1998-01-06
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[firstpage_image] =>[orig_patent_app_number] => 003359
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/003359 | Semiconductor device having a monotonically decreasing impurity concentration | Jan 5, 1998 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 2001-12-18
[patent_title] => 'Single transistor E2prom memory device with controlled erasing'
[patent_app_type] => 1
[patent_app_number] => 8/997407
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997407 | Single transistor E2prom memory device with controlled erasing | Dec 22, 1997 | Issued |
Array
(
[id] => 4408115
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/994107 | Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength | Dec 18, 1997 | Issued |