Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4350850 [patent_doc_number] => 06285054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings' [patent_app_type] => 1 [patent_app_number] => 9/052057 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285054.pdf [firstpage_image] =>[orig_patent_app_number] => 052057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052057
Trenched gate non-volatile semiconductor device with the source/drain regions spaced from the trench by sidewall dopings Mar 29, 1998 Issued
09/047438 COPPER METALIZATION WITH IMPROVED ELECTROMIGRATION RESISTANCE Mar 24, 1998 Abandoned
Array ( [id] => 4389975 [patent_doc_number] => 06262469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor' [patent_app_type] => 1 [patent_app_number] => 9/047237 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262469.pdf [firstpage_image] =>[orig_patent_app_number] => 047237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/047237
Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor Mar 24, 1998 Issued
Array ( [id] => 4257298 [patent_doc_number] => 06207991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same' [patent_app_type] => 1 [patent_app_number] => 9/045269 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207991.pdf [firstpage_image] =>[orig_patent_app_number] => 045269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045269
Integrated non-volatile and CMOS memories having substantially the same thickness gates and methods of forming the same Mar 19, 1998 Issued
Array ( [id] => 4302547 [patent_doc_number] => 06187634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Process for making an EEPROM active area castling' [patent_app_type] => 1 [patent_app_number] => 9/045737 [patent_app_country] => US [patent_app_date] => 1998-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4448 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187634.pdf [firstpage_image] =>[orig_patent_app_number] => 045737 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/045737
Process for making an EEPROM active area castling Mar 18, 1998 Issued
Array ( [id] => 4380574 [patent_doc_number] => 06261867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of making a package for microelectronic devices using iron oxide as a bonding agent' [patent_app_type] => 1 [patent_app_number] => 9/039058 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3113 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261867.pdf [firstpage_image] =>[orig_patent_app_number] => 039058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/039058
Method of making a package for microelectronic devices using iron oxide as a bonding agent Mar 12, 1998 Issued
09/037849 DUAL DIAMETER CONTACT PLUG AND METHOD OF MAKING Mar 9, 1998 Abandoned
Array ( [id] => 4185633 [patent_doc_number] => 06093606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Method of manufacture of vertical stacked gate flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/035049 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 30 [patent_no_of_words] => 3507 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093606.pdf [firstpage_image] =>[orig_patent_app_number] => 035049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035049
Method of manufacture of vertical stacked gate flash memory device Mar 4, 1998 Issued
09/034338 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN INTERLAYER INSULATING FILM FORMED UNDER A BONDING PAD AND ARRANGED TO PREVENT PEELING OF THE BONDING PAD Mar 3, 1998 Abandoned
09/026539 NONVOLATILE MEMORY DEVICES INCLUDING BIRD'S BEAK OXIDE AND METHODS FOR FABRICATING THE SAME Feb 18, 1998 Abandoned
Array ( [id] => 4277633 [patent_doc_number] => 06323510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45.degree. angles' [patent_app_type] => 1 [patent_app_number] => 9/023819 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6089 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323510.pdf [firstpage_image] =>[orig_patent_app_number] => 023819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023819
Semiconductor memory device having an array of memory cells including a select transistor and a storage capacitor wiring lines at 45.degree. angles Feb 12, 1998 Issued
Array ( [id] => 4222784 [patent_doc_number] => 06087700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Gate having a barrier of titanium silicide' [patent_app_type] => 1 [patent_app_number] => 9/021729 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1734 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087700.pdf [firstpage_image] =>[orig_patent_app_number] => 021729 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021729
Gate having a barrier of titanium silicide Feb 10, 1998 Issued
Array ( [id] => 1107666 [patent_doc_number] => 06808988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method for forming isolation in flash memory wafer' [patent_app_type] => B1 [patent_app_number] => 09/019409 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808988.pdf [firstpage_image] =>[orig_patent_app_number] => 09019409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019409
Method for forming isolation in flash memory wafer Feb 4, 1998 Issued
Array ( [id] => 4387036 [patent_doc_number] => 06294794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Non-linear optical device using quantum dots' [patent_app_type] => 1 [patent_app_number] => 9/018858 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 8890 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294794.pdf [firstpage_image] =>[orig_patent_app_number] => 018858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018858
Non-linear optical device using quantum dots Feb 3, 1998 Issued
Array ( [id] => 4163513 [patent_doc_number] => 06114760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Ball grid array (BGA) semiconductor package member' [patent_app_type] => 1 [patent_app_number] => 9/010149 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 53 [patent_no_of_words] => 5009 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114760.pdf [firstpage_image] =>[orig_patent_app_number] => 010149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010149
Ball grid array (BGA) semiconductor package member Jan 20, 1998 Issued
Array ( [id] => 4162640 [patent_doc_number] => 06157056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays' [patent_app_type] => 1 [patent_app_number] => 9/008627 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 55 [patent_no_of_words] => 10518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157056.pdf [firstpage_image] =>[orig_patent_app_number] => 008627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008627
Semiconductor memory device having a plurality of memory cell transistors arranged to constitute memory cell arrays Jan 15, 1998 Issued
Array ( [id] => 4139941 [patent_doc_number] => 06121673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Leadframe finger support' [patent_app_type] => 1 [patent_app_number] => 9/006237 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 858 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121673.pdf [firstpage_image] =>[orig_patent_app_number] => 006237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006237
Leadframe finger support Jan 12, 1998 Issued
Array ( [id] => 4145160 [patent_doc_number] => 06060745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Semiconductor device having a monotonically decreasing impurity concentration' [patent_app_type] => 1 [patent_app_number] => 9/003359 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 7240 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060745.pdf [firstpage_image] =>[orig_patent_app_number] => 003359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003359
Semiconductor device having a monotonically decreasing impurity concentration Jan 5, 1998 Issued
Array ( [id] => 4326087 [patent_doc_number] => 06331724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Single transistor E2prom memory device with controlled erasing' [patent_app_type] => 1 [patent_app_number] => 8/997407 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 6366 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331724.pdf [firstpage_image] =>[orig_patent_app_number] => 997407 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997407
Single transistor E2prom memory device with controlled erasing Dec 22, 1997 Issued
Array ( [id] => 4408115 [patent_doc_number] => 06228663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength' [patent_app_type] => 1 [patent_app_number] => 8/994107 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2627 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228663.pdf [firstpage_image] =>[orig_patent_app_number] => 994107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994107
Method of forming semiconductor devices using gate insulator thickness and channel length for controlling drive current strength Dec 18, 1997 Issued
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