Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4163599 [patent_doc_number] => 06114766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Integrated circuit with metal features presenting a larger landing area for vias' [patent_app_type] => 1 [patent_app_number] => 8/992839 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4098 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114766.pdf [firstpage_image] =>[orig_patent_app_number] => 992839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992839
Integrated circuit with metal features presenting a larger landing area for vias Dec 17, 1997 Issued
Array ( [id] => 1257197 [patent_doc_number] => 06667511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration' [patent_app_type] => B1 [patent_app_number] => 08/993368 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 38 [patent_no_of_words] => 6893 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667511.pdf [firstpage_image] =>[orig_patent_app_number] => 08993368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993368
NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration Dec 17, 1997 Issued
Array ( [id] => 1386421 [patent_doc_number] => 06555867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Flash memory gate coupling using HSG polysilicon' [patent_app_type] => B1 [patent_app_number] => 08/991448 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3007 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555867.pdf [firstpage_image] =>[orig_patent_app_number] => 08991448 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991448
Flash memory gate coupling using HSG polysilicon Dec 15, 1997 Issued
Array ( [id] => 4123087 [patent_doc_number] => 06072191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Interlevel dielectric thickness monitor for complex semiconductor chips' [patent_app_type] => 1 [patent_app_number] => 8/991299 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072191.pdf [firstpage_image] =>[orig_patent_app_number] => 991299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991299
Interlevel dielectric thickness monitor for complex semiconductor chips Dec 15, 1997 Issued
Array ( [id] => 3952812 [patent_doc_number] => 05998829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Non-volatile memory device incorporating a dual channel structure' [patent_app_type] => 1 [patent_app_number] => 8/985679 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3549 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998829.pdf [firstpage_image] =>[orig_patent_app_number] => 985679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985679
Non-volatile memory device incorporating a dual channel structure Dec 4, 1997 Issued
Array ( [id] => 4297269 [patent_doc_number] => 06236079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Dynamic semiconductor memory device having a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 8/982478 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 7610 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236079.pdf [firstpage_image] =>[orig_patent_app_number] => 982478 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982478
Dynamic semiconductor memory device having a trench capacitor Dec 1, 1997 Issued
Array ( [id] => 4136621 [patent_doc_number] => 06030548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'SRAM memory device having reduced size' [patent_app_type] => 1 [patent_app_number] => 8/978002 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 6114 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030548.pdf [firstpage_image] =>[orig_patent_app_number] => 978002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978002
SRAM memory device having reduced size Nov 24, 1997 Issued
08/970419 SURFACE MOUNTING TYPE SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME Nov 13, 1997 Abandoned
08/966899 MEMORY CAPACITOR WITH POLYMER-CONTAINING MEMORY DIELECTRIC Nov 9, 1997 Abandoned
Array ( [id] => 3943935 [patent_doc_number] => 05973346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Low-profile shallow trench double polysilicon capacitor' [patent_app_type] => 1 [patent_app_number] => 8/966737 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5209 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973346.pdf [firstpage_image] =>[orig_patent_app_number] => 966737 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966737
Low-profile shallow trench double polysilicon capacitor Nov 9, 1997 Issued
Array ( [id] => 4050444 [patent_doc_number] => 05943572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Electrically writable and erasable read-only memory cell arrangement and method for its production' [patent_app_type] => 1 [patent_app_number] => 8/952168 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5265 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943572.pdf [firstpage_image] =>[orig_patent_app_number] => 952168 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/952168
Electrically writable and erasable read-only memory cell arrangement and method for its production Nov 5, 1997 Issued
08/962143 DIE-INTEGRAL DECOUPLING CAPACITOR AND SEMICONDUCTOR DIE INCLUDING SAME Oct 30, 1997 Abandoned
Array ( [id] => 3865636 [patent_doc_number] => 05796135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/960142 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 4237 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796135.pdf [firstpage_image] =>[orig_patent_app_number] => 960142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960142
Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip Oct 28, 1997 Issued
Array ( [id] => 3815838 [patent_doc_number] => 05811862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Semiconductor device having a mask programmable memory and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/963118 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 7729 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811862.pdf [firstpage_image] =>[orig_patent_app_number] => 963118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963118
Semiconductor device having a mask programmable memory and manufacturing method thereof Oct 27, 1997 Issued
Array ( [id] => 4139404 [patent_doc_number] => 06121638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Multi-layer structured nitride-based semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/955747 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 10294 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121638.pdf [firstpage_image] =>[orig_patent_app_number] => 955747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955747
Multi-layer structured nitride-based semiconductor devices Oct 21, 1997 Issued
08/950757 SEMICONDUCTOR DEVICE HAVING A WIRING LAYER OF COPPER Oct 14, 1997 Abandoned
Array ( [id] => 4410410 [patent_doc_number] => 06271539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Electrical diagnostic technique for silicon plasma-etch induced damage characterization' [patent_app_type] => 1 [patent_app_number] => 8/950000 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3686 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271539.pdf [firstpage_image] =>[orig_patent_app_number] => 950000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/950000
Electrical diagnostic technique for silicon plasma-etch induced damage characterization Oct 13, 1997 Issued
Array ( [id] => 4139661 [patent_doc_number] => 06121654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Memory device having a crested tunnel barrier' [patent_app_type] => 1 [patent_app_number] => 8/949217 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2458 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121654.pdf [firstpage_image] =>[orig_patent_app_number] => 949217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949217
Memory device having a crested tunnel barrier Oct 9, 1997 Issued
Array ( [id] => 3953409 [patent_doc_number] => 05998869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'High storage capacity, wide data input/output channel, static random access memory device' [patent_app_type] => 1 [patent_app_number] => 8/938629 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3220 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998869.pdf [firstpage_image] =>[orig_patent_app_number] => 938629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938629
High storage capacity, wide data input/output channel, static random access memory device Sep 25, 1997 Issued
Array ( [id] => 4161766 [patent_doc_number] => 06104083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Lead frame used for semiconductor chips of different bit configurations' [patent_app_type] => 1 [patent_app_number] => 8/936419 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3579 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104083.pdf [firstpage_image] =>[orig_patent_app_number] => 936419 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936419
Lead frame used for semiconductor chips of different bit configurations Sep 23, 1997 Issued
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