Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 4163599
[patent_doc_number] => 06114766
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Integrated circuit with metal features presenting a larger landing area for vias'
[patent_app_type] => 1
[patent_app_number] => 8/992839
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[patent_app_date] => 1997-12-18
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Array
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[patent_doc_number] => 06667511
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[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration'
[patent_app_type] => B1
[patent_app_number] => 08/993368
[patent_app_country] => US
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Array
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[id] => 1386421
[patent_doc_number] => 06555867
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Flash memory gate coupling using HSG polysilicon'
[patent_app_type] => B1
[patent_app_number] => 08/991448
[patent_app_country] => US
[patent_app_date] => 1997-12-16
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Array
(
[id] => 4123087
[patent_doc_number] => 06072191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Interlevel dielectric thickness monitor for complex semiconductor chips'
[patent_app_type] => 1
[patent_app_number] => 8/991299
[patent_app_country] => US
[patent_app_date] => 1997-12-16
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Array
(
[id] => 3952812
[patent_doc_number] => 05998829
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Non-volatile memory device incorporating a dual channel structure'
[patent_app_type] => 1
[patent_app_number] => 8/985679
[patent_app_country] => US
[patent_app_date] => 1997-12-05
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[pdf_file] => patents/05/998/05998829.pdf
[firstpage_image] =>[orig_patent_app_number] => 985679
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/985679 | Non-volatile memory device incorporating a dual channel structure | Dec 4, 1997 | Issued |
Array
(
[id] => 4297269
[patent_doc_number] => 06236079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Dynamic semiconductor memory device having a trench capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/982478
[patent_app_country] => US
[patent_app_date] => 1997-12-02
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Array
(
[id] => 4136621
[patent_doc_number] => 06030548
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'SRAM memory device having reduced size'
[patent_app_type] => 1
[patent_app_number] => 8/978002
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/030/06030548.pdf
[firstpage_image] =>[orig_patent_app_number] => 978002
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978002 | SRAM memory device having reduced size | Nov 24, 1997 | Issued |
08/970419 | SURFACE MOUNTING TYPE SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME | Nov 13, 1997 | Abandoned |
08/966899 | MEMORY CAPACITOR WITH POLYMER-CONTAINING MEMORY DIELECTRIC | Nov 9, 1997 | Abandoned |
Array
(
[id] => 3943935
[patent_doc_number] => 05973346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Low-profile shallow trench double polysilicon capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/966737
[patent_app_country] => US
[patent_app_date] => 1997-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/973/05973346.pdf
[firstpage_image] =>[orig_patent_app_number] => 966737
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/966737 | Low-profile shallow trench double polysilicon capacitor | Nov 9, 1997 | Issued |
Array
(
[id] => 4050444
[patent_doc_number] => 05943572
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-24
[patent_title] => 'Electrically writable and erasable read-only memory cell arrangement and method for its production'
[patent_app_type] => 1
[patent_app_number] => 8/952168
[patent_app_country] => US
[patent_app_date] => 1997-11-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/943/05943572.pdf
[firstpage_image] =>[orig_patent_app_number] => 952168
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/952168 | Electrically writable and erasable read-only memory cell arrangement and method for its production | Nov 5, 1997 | Issued |
08/962143 | DIE-INTEGRAL DECOUPLING CAPACITOR AND SEMICONDUCTOR DIE INCLUDING SAME | Oct 30, 1997 | Abandoned |
Array
(
[id] => 3865636
[patent_doc_number] => 05796135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Process to fabricate stacked capacitor dram and low power thin film transistor sram devices on a single semiconductor chip'
[patent_app_type] => 1
[patent_app_number] => 8/960142
[patent_app_country] => US
[patent_app_date] => 1997-10-29
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Array
(
[id] => 3815838
[patent_doc_number] => 05811862
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Semiconductor device having a mask programmable memory and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/963118
[patent_app_country] => US
[patent_app_date] => 1997-10-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/963118 | Semiconductor device having a mask programmable memory and manufacturing method thereof | Oct 27, 1997 | Issued |
Array
(
[id] => 4139404
[patent_doc_number] => 06121638
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Multi-layer structured nitride-based semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/955747
[patent_app_country] => US
[patent_app_date] => 1997-10-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 955747
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/955747 | Multi-layer structured nitride-based semiconductor devices | Oct 21, 1997 | Issued |
08/950757 | SEMICONDUCTOR DEVICE HAVING A WIRING LAYER OF COPPER | Oct 14, 1997 | Abandoned |
Array
(
[id] => 4410410
[patent_doc_number] => 06271539
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Electrical diagnostic technique for silicon plasma-etch induced damage characterization'
[patent_app_type] => 1
[patent_app_number] => 8/950000
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[firstpage_image] =>[orig_patent_app_number] => 950000
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/950000 | Electrical diagnostic technique for silicon plasma-etch induced damage characterization | Oct 13, 1997 | Issued |
Array
(
[id] => 4139661
[patent_doc_number] => 06121654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Memory device having a crested tunnel barrier'
[patent_app_type] => 1
[patent_app_number] => 8/949217
[patent_app_country] => US
[patent_app_date] => 1997-10-10
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[firstpage_image] =>[orig_patent_app_number] => 949217
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/949217 | Memory device having a crested tunnel barrier | Oct 9, 1997 | Issued |
Array
(
[id] => 3953409
[patent_doc_number] => 05998869
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'High storage capacity, wide data input/output channel, static random access memory device'
[patent_app_type] => 1
[patent_app_number] => 8/938629
[patent_app_country] => US
[patent_app_date] => 1997-09-26
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[firstpage_image] =>[orig_patent_app_number] => 938629
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/938629 | High storage capacity, wide data input/output channel, static random access memory device | Sep 25, 1997 | Issued |
Array
(
[id] => 4161766
[patent_doc_number] => 06104083
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Lead frame used for semiconductor chips of different bit configurations'
[patent_app_type] => 1
[patent_app_number] => 8/936419
[patent_app_country] => US
[patent_app_date] => 1997-09-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/936419 | Lead frame used for semiconductor chips of different bit configurations | Sep 23, 1997 | Issued |