Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4258244 [patent_doc_number] => 06204122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios' [patent_app_type] => 1 [patent_app_number] => 8/932641 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 43 [patent_no_of_words] => 5685 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204122.pdf [firstpage_image] =>[orig_patent_app_number] => 932641 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932641
Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios Sep 16, 1997 Issued
Array ( [id] => 1553021 [patent_doc_number] => 06400012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Heat sink for use in cooling an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 08/932308 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400012.pdf [firstpage_image] =>[orig_patent_app_number] => 08932308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932308
Heat sink for use in cooling an integrated circuit Sep 16, 1997 Issued
Array ( [id] => 4376426 [patent_doc_number] => 06288421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8\" wafer' [patent_app_type] => 1 [patent_app_number] => 8/929585 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 13403 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288421.pdf [firstpage_image] =>[orig_patent_app_number] => 929585 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929585
Semiconductor memory circuitry including die sites for 16M to 17M memory cells in an 8" wafer Sep 14, 1997 Issued
Array ( [id] => 4038535 [patent_doc_number] => 05942778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Switching transistor and capacitor for memory cell' [patent_app_type] => 1 [patent_app_number] => 8/928078 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5324 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942778.pdf [firstpage_image] =>[orig_patent_app_number] => 928078 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928078
Switching transistor and capacitor for memory cell Sep 11, 1997 Issued
Array ( [id] => 3885684 [patent_doc_number] => 05798559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Integrated circuit structure having an air dielectric and dielectric support pillars' [patent_app_type] => 1 [patent_app_number] => 8/922953 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798559.pdf [firstpage_image] =>[orig_patent_app_number] => 922953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922953
Integrated circuit structure having an air dielectric and dielectric support pillars Sep 2, 1997 Issued
Array ( [id] => 3944020 [patent_doc_number] => 05973352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Ultra high density flash memory having vertically stacked devices' [patent_app_type] => 1 [patent_app_number] => 8/915197 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7003 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973352.pdf [firstpage_image] =>[orig_patent_app_number] => 915197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915197
Ultra high density flash memory having vertically stacked devices Aug 19, 1997 Issued
08/908718 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INDIVIDUALLY OPTIMIZED BI-POLAR AND MOS TRANSISTORS Aug 7, 1997 Abandoned
08/905048 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jul 31, 1997 Abandoned
08/900328 MOS CAPACITOR WITH WIDE VOLTAGE AND FREQUENCY OPERATING RANGES Jul 24, 1997 Abandoned
Array ( [id] => 4094597 [patent_doc_number] => 06133597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Biasing an integrated circuit well with a transistor electrode' [patent_app_type] => 1 [patent_app_number] => 8/900560 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5191 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133597.pdf [firstpage_image] =>[orig_patent_app_number] => 900560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900560
Biasing an integrated circuit well with a transistor electrode Jul 24, 1997 Issued
Array ( [id] => 4075827 [patent_doc_number] => 06069380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Single-electron floating-gate MOS memory' [patent_app_type] => 1 [patent_app_number] => 8/900947 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 6990 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069380.pdf [firstpage_image] =>[orig_patent_app_number] => 900947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/900947
Single-electron floating-gate MOS memory Jul 24, 1997 Issued
Array ( [id] => 4009400 [patent_doc_number] => 06005267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'MES/MIS FET with split-gate RF input' [patent_app_type] => 1 [patent_app_number] => 8/888526 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4916 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005267.pdf [firstpage_image] =>[orig_patent_app_number] => 888526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888526
MES/MIS FET with split-gate RF input Jul 6, 1997 Issued
Array ( [id] => 4239211 [patent_doc_number] => 06118158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Static random access memory device having a memory cell array region in which a unit cell is arranged in a matrix' [patent_app_type] => 1 [patent_app_number] => 8/883348 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 7284 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 784 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118158.pdf [firstpage_image] =>[orig_patent_app_number] => 883348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883348
Static random access memory device having a memory cell array region in which a unit cell is arranged in a matrix Jun 25, 1997 Issued
Array ( [id] => 4139531 [patent_doc_number] => 06121647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Film structure, electronic device, recording medium, and process of preparing ferroelectric thin films' [patent_app_type] => 1 [patent_app_number] => 8/883456 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 18101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121647.pdf [firstpage_image] =>[orig_patent_app_number] => 883456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883456
Film structure, electronic device, recording medium, and process of preparing ferroelectric thin films Jun 25, 1997 Issued
Array ( [id] => 4212163 [patent_doc_number] => 06028326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Thin film transistor including a catalytic element for promoting crystallization of a semiconductor film' [patent_app_type] => 1 [patent_app_number] => 8/881257 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3975 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028326.pdf [firstpage_image] =>[orig_patent_app_number] => 881257 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881257
Thin film transistor including a catalytic element for promoting crystallization of a semiconductor film Jun 23, 1997 Issued
Array ( [id] => 4176659 [patent_doc_number] => 06140684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 8/881342 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4789 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140684.pdf [firstpage_image] =>[orig_patent_app_number] => 881342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881342
SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers Jun 23, 1997 Issued
Array ( [id] => 4067674 [patent_doc_number] => 05895949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Semiconductor device having inversion inducing gate' [patent_app_type] => 1 [patent_app_number] => 8/879790 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 6127 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895949.pdf [firstpage_image] =>[orig_patent_app_number] => 879790 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879790
Semiconductor device having inversion inducing gate Jun 19, 1997 Issued
Array ( [id] => 4148203 [patent_doc_number] => 06031287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Contact structure and memory element incorporating the same' [patent_app_type] => 1 [patent_app_number] => 8/878450 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 41 [patent_no_of_words] => 9832 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031287.pdf [firstpage_image] =>[orig_patent_app_number] => 878450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878450
Contact structure and memory element incorporating the same Jun 17, 1997 Issued
Array ( [id] => 4140477 [patent_doc_number] => 06015985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Deep trench with enhanced sidewall surface area' [patent_app_type] => 1 [patent_app_number] => 8/877446 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 2732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015985.pdf [firstpage_image] =>[orig_patent_app_number] => 877446 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877446
Deep trench with enhanced sidewall surface area Jun 16, 1997 Issued
Array ( [id] => 1478914 [patent_doc_number] => 06344692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Highly integrated and reliable DRAM adapted for self-aligned contact' [patent_app_type] => B1 [patent_app_number] => 08/876908 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 49 [patent_no_of_words] => 14656 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344692.pdf [firstpage_image] =>[orig_patent_app_number] => 08876908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876908
Highly integrated and reliable DRAM adapted for self-aligned contact Jun 15, 1997 Issued
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