Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 4053926
[patent_doc_number] => 05869858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Semiconductor device for reducing variations in characteristics of the device'
[patent_app_type] => 1
[patent_app_number] => 8/614538
[patent_app_country] => US
[patent_app_date] => 1996-03-13
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/869/05869858.pdf
[firstpage_image] =>[orig_patent_app_number] => 614538
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/614538 | Semiconductor device for reducing variations in characteristics of the device | Mar 12, 1996 | Issued |
Array
(
[id] => 3895906
[patent_doc_number] => 05834807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Nonvolatile memory device having an improved integration and reduced contact failure'
[patent_app_type] => 1
[patent_app_number] => 8/615064
[patent_app_country] => US
[patent_app_date] => 1996-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 31
[patent_no_of_words] => 7058
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[pdf_file] => patents/05/834/05834807.pdf
[firstpage_image] =>[orig_patent_app_number] => 615064
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/615064 | Nonvolatile memory device having an improved integration and reduced contact failure | Mar 12, 1996 | Issued |
08/611408 | SEMICONDUCTOR APPARATUS AND PRODUCTION METHOD FOR THE SAME | Mar 5, 1996 | Abandoned |
Array
(
[id] => 4132813
[patent_doc_number] => 06127734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Semiconductor device comprising a contact hole of varying width thru multiple insulating layers'
[patent_app_type] => 1
[patent_app_number] => 8/607034
[patent_app_country] => US
[patent_app_date] => 1996-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
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[patent_no_of_words] => 11023
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[pdf_file] => patents/06/127/06127734.pdf
[firstpage_image] =>[orig_patent_app_number] => 607034
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607034 | Semiconductor device comprising a contact hole of varying width thru multiple insulating layers | Feb 25, 1996 | Issued |
Array
(
[id] => 3776083
[patent_doc_number] => 05773875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'High performance, low thermal loss, bi-temperature superconductive device'
[patent_app_type] => 1
[patent_app_number] => 8/606177
[patent_app_country] => US
[patent_app_date] => 1996-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3559
[patent_no_of_claims] => 38
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[pdf_file] => patents/05/773/05773875.pdf
[firstpage_image] =>[orig_patent_app_number] => 606177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/606177 | High performance, low thermal loss, bi-temperature superconductive device | Feb 22, 1996 | Issued |
Array
(
[id] => 3845186
[patent_doc_number] => 05744825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Composite structure for an electronic component comprising a growth substrate, a diamond layer, and an intermediate layer therebetween'
[patent_app_type] => 1
[patent_app_number] => 8/594038
[patent_app_country] => US
[patent_app_date] => 1996-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4978
[patent_no_of_claims] => 6
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/744/05744825.pdf
[firstpage_image] =>[orig_patent_app_number] => 594038
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594038 | Composite structure for an electronic component comprising a growth substrate, a diamond layer, and an intermediate layer therebetween | Jan 29, 1996 | Issued |
Array
(
[id] => 4309601
[patent_doc_number] => 06326640
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Organic thin film transistor with enhanced carrier mobility'
[patent_app_type] => 1
[patent_app_number] => 8/592930
[patent_app_country] => US
[patent_app_date] => 1996-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 7
[patent_no_of_words] => 2644
[patent_no_of_claims] => 24
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[pdf_file] => patents/06/326/06326640.pdf
[firstpage_image] =>[orig_patent_app_number] => 592930
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/592930 | Organic thin film transistor with enhanced carrier mobility | Jan 28, 1996 | Issued |
08/590566 | THIN FILM CAPACITOR | Jan 25, 1996 | Abandoned |
08/590782 | P-N BUFFERED MESA SCHOTTKY BARRIER DIODE | Jan 23, 1996 | Abandoned |
Array
(
[id] => 3865431
[patent_doc_number] => 05796120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Tunnel thin film electroluminescent device'
[patent_app_type] => 1
[patent_app_number] => 8/577976
[patent_app_country] => US
[patent_app_date] => 1995-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5651
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796120.pdf
[firstpage_image] =>[orig_patent_app_number] => 577976
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/577976 | Tunnel thin film electroluminescent device | Dec 27, 1995 | Issued |
08/577186 | DIE CAPACITOR FOR CHIP ON BOARD TECHNOLOGY | Dec 21, 1995 | Abandoned |
Array
(
[id] => 3834622
[patent_doc_number] => 05760456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Integrated circuit compatible planar inductors with increased Q'
[patent_app_type] => 1
[patent_app_number] => 8/576024
[patent_app_country] => US
[patent_app_date] => 1995-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 4568
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760456.pdf
[firstpage_image] =>[orig_patent_app_number] => 576024
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/576024 | Integrated circuit compatible planar inductors with increased Q | Dec 20, 1995 | Issued |
08/570946 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INDIVIDUALLY OPTIMIZED BI-POLAR AND MOS TRANSISTORS | Dec 11, 1995 | Abandoned |
08/565166 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THEREOF | Nov 29, 1995 | Abandoned |
08/559108 | VERTICAL CHANNEL MASKED ROM MEMORY CELL TECHNOLOGY WITH EPITAXY AND METHOD FOR MAKING THE SAME | Nov 15, 1995 | Abandoned |
Array
(
[id] => 3740873
[patent_doc_number] => 05698880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Semiconductor device having a groove with a curved part formed on its side surface'
[patent_app_type] => 1
[patent_app_number] => 8/539380
[patent_app_country] => US
[patent_app_date] => 1995-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 40
[patent_no_of_words] => 6999
[patent_no_of_claims] => 7
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/698/05698880.pdf
[firstpage_image] =>[orig_patent_app_number] => 539380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/539380 | Semiconductor device having a groove with a curved part formed on its side surface | Oct 4, 1995 | Issued |
Array
(
[id] => 3812631
[patent_doc_number] => 05831329
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Layered system with an electrically activatable layer'
[patent_app_type] => 1
[patent_app_number] => 8/532638
[patent_app_country] => US
[patent_app_date] => 1995-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2998
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/831/05831329.pdf
[firstpage_image] =>[orig_patent_app_number] => 532638
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/532638 | Layered system with an electrically activatable layer | Oct 2, 1995 | Issued |
08/537305 | MES/MIS FET | Sep 28, 1995 | Abandoned |
Array
(
[id] => 3892335
[patent_doc_number] => 05777358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Stacked capacitor semiconductor memory device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/535857
[patent_app_country] => US
[patent_app_date] => 1995-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5487
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[pdf_file] => patents/05/777/05777358.pdf
[firstpage_image] =>[orig_patent_app_number] => 535857
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/535857 | Stacked capacitor semiconductor memory device and method for fabricating the same | Sep 27, 1995 | Issued |
Array
(
[id] => 3750790
[patent_doc_number] => 05717244
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Semiconductor device having layers with varying lifetime characteristics'
[patent_app_type] => 1
[patent_app_number] => 8/533753
[patent_app_country] => US
[patent_app_date] => 1995-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717244.pdf
[firstpage_image] =>[orig_patent_app_number] => 533753
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/533753 | Semiconductor device having layers with varying lifetime characteristics | Sep 25, 1995 | Issued |