
Paul N. Dickson
Supervisory Patent Examiner (ID: 8782, Phone: (571)272-7742 , Office: P/3616 )
| Most Active Art Unit | 3106 |
| Art Unit(s) | 3614, 3618, 3600, 3106, 3616, 3611, 2899 |
| Total Applications | 1181 |
| Issued Applications | 976 |
| Pending Applications | 84 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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