Search

Paul N. Dickson

Supervisory Patent Examiner (ID: 8782, Phone: (571)272-7742 , Office: P/3616 )

Most Active Art Unit
3106
Art Unit(s)
3614, 3618, 3600, 3106, 3616, 3611, 2899
Total Applications
1181
Issued Applications
976
Pending Applications
84
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20704017 [patent_doc_number] => 12626732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Semiconductor structure including memory signal transmission line in backside redistribution [patent_app_type] => utility [patent_app_number] => 18/588008 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588008
Semiconductor structure including memory signal transmission line in backside redistribution Feb 26, 2024 Issued
Array ( [id] => 19886675 [patent_doc_number] => 12272399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-08 [patent_title] => Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement [patent_app_type] => utility [patent_app_number] => 18/587443 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587443
Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement Feb 25, 2024 Issued
Array ( [id] => 19237072 [patent_doc_number] => 20240194267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY DEVICE RELATED TO PERFORMING A PROGRAM OPERATION ON MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/583632 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583632
Memory device related to performing a program operation on memory cells Feb 20, 2024 Issued
Array ( [id] => 19740987 [patent_doc_number] => 12217826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Memory array test structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/443997 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 78 [patent_no_of_words] => 15058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443997
Memory array test structure and method of forming the same Feb 15, 2024 Issued
Array ( [id] => 19406853 [patent_doc_number] => 20240290364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DEVICE AND METHOD FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 18/441110 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441110
Device and method for in-memory computing Feb 13, 2024 Issued
Array ( [id] => 20538553 [patent_doc_number] => 12555632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => High density embedded flash cell array structure [patent_app_type] => utility [patent_app_number] => 18/439744 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439744
High density embedded flash cell array structure Feb 11, 2024 Issued
Array ( [id] => 19406881 [patent_doc_number] => 20240290392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DECK-BASED ERASE FUNCTION [patent_app_type] => utility [patent_app_number] => 18/437419 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437419 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437419
Deck-based erase function Feb 8, 2024 Issued
Array ( [id] => 20648184 [patent_doc_number] => 12603134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => NOR memory cell with floating gate [patent_app_type] => utility [patent_app_number] => 18/429938 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 74 [patent_no_of_words] => 9419 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429938
NOR memory cell with floating gate Jan 31, 2024 Issued
Array ( [id] => 20139211 [patent_doc_number] => 20250246255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => CROSSBAR CIRCUITS INCLUDING RRAM DEVICES WITH MINIMIZED WRITE DISTURBANCES [patent_app_type] => utility [patent_app_number] => 18/429313 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429313
Crossbar circuits including RRAM devices with minimized write disturbances Jan 30, 2024 Issued
Array ( [id] => 20141271 [patent_doc_number] => 20250248315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => DOMAIN WALL MOVEMENT ELEMENT, MAGNETORESISTIVE ELEMENT, AND MAGNETIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/426880 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3657 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426880 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426880
Domain wall movement element, magnetoresistive element, and magnetic array Jan 29, 2024 Issued
Array ( [id] => 19384323 [patent_doc_number] => 20240274193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => 3D CELL AND ARRAY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/424700 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424700
3D CELL AND ARRAY STRUCTURES Jan 25, 2024 Pending
Array ( [id] => 20139191 [patent_doc_number] => 20250246235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => HIGH VOLTAGE COLUMN MULTIPLEXOR [patent_app_type] => utility [patent_app_number] => 18/423542 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423542
High voltage column multiplexor Jan 25, 2024 Issued
Array ( [id] => 20019275 [patent_doc_number] => 20250157497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MEMORY, STORAGE SYSTEMS, AND OPERATION METHODS OF MEMORY [patent_app_type] => utility [patent_app_number] => 18/422945 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422945
Memory, storage systems, and operation methods of memory Jan 24, 2024 Issued
Array ( [id] => 20611015 [patent_doc_number] => 12586619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Integrated circuit device and methods [patent_app_type] => utility [patent_app_number] => 18/421683 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 33 [patent_no_of_words] => 16322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421683
Integrated circuit device and methods Jan 23, 2024 Issued
Array ( [id] => 19321214 [patent_doc_number] => 20240242760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => REFERENCE VOLTAGE ADJUSTMENT FOR WORD LINE GROUPS [patent_app_type] => utility [patent_app_number] => 18/421729 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421729 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421729
Reference voltage adjustment for word line groups Jan 23, 2024 Issued
Array ( [id] => 20649522 [patent_doc_number] => 12604485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Cross point array architecture for multiple decks [patent_app_type] => utility [patent_app_number] => 18/416763 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416763 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416763
Cross point array architecture for multiple decks Jan 17, 2024 Issued
Array ( [id] => 20104630 [patent_doc_number] => 20250234566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY DEVICE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/414502 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/414502
Memory device and method for operating the same Jan 16, 2024 Issued
Array ( [id] => 19252504 [patent_doc_number] => 20240203501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => PROGRAMMING OPERATION USING CACHE REGISTER RELEASE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/404282 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404282
Programming operation using cache register release in a memory sub-system Jan 3, 2024 Issued
Array ( [id] => 19566698 [patent_doc_number] => 12141470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Feedback for multi-level signaling in a memory device [patent_app_type] => utility [patent_app_number] => 18/403512 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 23290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403512
Feedback for multi-level signaling in a memory device Jan 2, 2024 Issued
Array ( [id] => 19321206 [patent_doc_number] => 20240242752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => TECHNIQUES FOR DATA REFRESH BASED ON ENVIRONMENTAL CONDITIONS [patent_app_type] => utility [patent_app_number] => 18/403468 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403468
Techniques for data refresh based on environmental conditions Jan 2, 2024 Issued
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