Search

Paul N. Dickson

Supervisory Patent Examiner (ID: 8782, Phone: (571)272-7742 , Office: P/3616 )

Most Active Art Unit
3106
Art Unit(s)
3614, 3618, 3600, 3106, 3616, 3611, 2899
Total Applications
1181
Issued Applications
976
Pending Applications
84
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19610798 [patent_doc_number] => 12159678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/363872 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 51 [patent_no_of_words] => 23997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363872
Semiconductor memory device Aug 1, 2023 Issued
Array ( [id] => 19037808 [patent_doc_number] => 20240087623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => MEMORY DEVICE WITH SELECTIVE PRECHARGING [patent_app_type] => utility [patent_app_number] => 18/362662 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362662 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362662
Memory device with selective precharging Jul 30, 2023 Issued
Array ( [id] => 19639512 [patent_doc_number] => 12170125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Memory device and electronic device [patent_app_type] => utility [patent_app_number] => 18/362752 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362752
Memory device and electronic device Jul 30, 2023 Issued
Array ( [id] => 19507623 [patent_doc_number] => 12119052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Low voltage memory device [patent_app_type] => utility [patent_app_number] => 18/362736 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362736 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362736
Low voltage memory device Jul 30, 2023 Issued
Array ( [id] => 19582379 [patent_doc_number] => 12148505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Memory array staircase structure [patent_app_type] => utility [patent_app_number] => 18/362685 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 83 [patent_no_of_words] => 14627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362685
Memory array staircase structure Jul 30, 2023 Issued
Array ( [id] => 20117454 [patent_doc_number] => 12367160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => System and method for valid window maximization in toggle mode link using systematic skew addition to compensate for SSO and crosstalk [patent_app_type] => utility [patent_app_number] => 18/360674 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 20 [patent_no_of_words] => 15629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360674
System and method for valid window maximization in toggle mode link using systematic skew addition to compensate for SSO and crosstalk Jul 26, 2023 Issued
Array ( [id] => 20118216 [patent_doc_number] => 12367931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Stacked column floorplan for NAND [patent_app_type] => utility [patent_app_number] => 18/358598 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 12441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358598
Stacked column floorplan for NAND Jul 24, 2023 Issued
Array ( [id] => 19964662 [patent_doc_number] => 12334177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/225916 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 42 [patent_no_of_words] => 5984 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225916
Semiconductor memory device Jul 24, 2023 Issued
Array ( [id] => 19573671 [patent_doc_number] => 20240377963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SLOW PROGRAMMING ON WEAK WORD LINES OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/357737 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357737 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357737
Slow programming on weak word lines of a memory device Jul 23, 2023 Issued
Array ( [id] => 20331378 [patent_doc_number] => 12461653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Fast look ahead read for non-volatile memory by removing pre-read redundancy [patent_app_type] => utility [patent_app_number] => 18/225320 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 34 [patent_no_of_words] => 13284 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18225320 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/225320
Fast look ahead read for non-volatile memory by removing pre-read redundancy Jul 23, 2023 Issued
Array ( [id] => 19191143 [patent_doc_number] => 20240170056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => Channel Circuit with Trained Neural Network Noise Mixture Estimator [patent_app_type] => utility [patent_app_number] => 18/354178 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354178
Channel circuit with trained neural network noise mixture estimator Jul 17, 2023 Issued
Array ( [id] => 19321218 [patent_doc_number] => 20240242764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO [patent_app_type] => utility [patent_app_number] => 18/222735 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222735 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/222735
PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO Jul 16, 2023 Pending
Array ( [id] => 20117427 [patent_doc_number] => 12367133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Apparatuses and methods for training operations [patent_app_type] => utility [patent_app_number] => 18/353639 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353639
Apparatuses and methods for training operations Jul 16, 2023 Issued
Array ( [id] => 19972898 [patent_doc_number] => 12341523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Delay control circuit, semiconductor memory device, and delay control method [patent_app_type] => utility [patent_app_number] => 18/347935 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347935 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347935
Delay control circuit, semiconductor memory device, and delay control method Jul 5, 2023 Issued
Array ( [id] => 18757637 [patent_doc_number] => 20230361100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MEMORY CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/346856 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346856
Memory circuits Jul 4, 2023 Issued
Array ( [id] => 19493355 [patent_doc_number] => 12112071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Nonvolatile memory device supporting high-efficiency I/O interface [patent_app_type] => utility [patent_app_number] => 18/217063 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/217063
Nonvolatile memory device supporting high-efficiency I/O interface Jun 29, 2023 Issued
Array ( [id] => 20119756 [patent_doc_number] => 12369497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Magnetoresistive random access memory device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/216610 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216610
Magnetoresistive random access memory device and method for fabricating the same Jun 29, 2023 Issued
Array ( [id] => 20266810 [patent_doc_number] => 12437806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/344058 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 2809 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344058
Semiconductor device and operating method thereof Jun 28, 2023 Issued
Array ( [id] => 18730131 [patent_doc_number] => 20230344429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR DEVICE RELATED TO CALIBRATING TERMINATION RESISTANCE [patent_app_type] => utility [patent_app_number] => 18/343537 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343537
Semiconductor device related to calibrating termination resistance Jun 27, 2023 Issued
Array ( [id] => 18728019 [patent_doc_number] => 20230342312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => STORAGE DEVICE AND COMPUTER DEVICE [patent_app_type] => utility [patent_app_number] => 18/342252 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342252
STORAGE DEVICE AND COMPUTER DEVICE Jun 26, 2023 Abandoned
Menu