Pauline Vu

Array ( [id] => 11946045 [patent_doc_number] => 20170250197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'LAYOUT STRUCTURE FOR SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/592877 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3720 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13514313 [patent_doc_number] => 20180308699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => GATE FILL UTILIZING REPLACEMENT SPACER [patent_app_type] => utility [patent_app_number] => 15/491565 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11997538 [patent_doc_number] => 20170301692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'TRANSISTOR WITH CONTROLLED OVERLAP OF ACCESS REGIONS' [patent_app_type] => utility [patent_app_number] => 15/485246 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8400 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11983701 [patent_doc_number] => 20170287855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'VARIABLE HANDLE WAFER RESISTIVITY FOR SILICON-ON-INSULATOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/476252 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10765 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11983780 [patent_doc_number] => 20170287935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'VARIABLE BURIED OXIDE THICKNESS FOR SILICON-ON-INSULATOR DEVICES' [patent_app_type] => utility [patent_app_number] => 15/476248 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10765 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11983658 [patent_doc_number] => 20170287813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'BODY CONTACTS FOR FIELD-EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/475510 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14525939 [patent_doc_number] => 10340240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Mechanisms for forming post-passivation interconnect structure [patent_app_type] => utility [patent_app_number] => 15/470341 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3944 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12631434 [patent_doc_number] => 20180102308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 15/446589 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15446589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14525999 [patent_doc_number] => 10340270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Integrated circuit having FinFETS with different fin profiles [patent_app_type] => utility [patent_app_number] => 15/442299 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 3074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11946164 [patent_doc_number] => 20170250315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'DOT MATRIX LIGHT-EMITTING DIODE BACKLIGHTING LIGHT SOURCE FOR A WAFER-LEVEL MICRODISPLAY AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/439574 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4035 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11623290 [patent_doc_number] => 20170133478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Transistors, Memory Cells and Semiconductor Constructions' [patent_app_type] => utility [patent_app_number] => 15/411886 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4402 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921331 [patent_doc_number] => 10204789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Manufacturing method of semiconductor device and semiconductor device [patent_app_type] => utility [patent_app_number] => 15/404463 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 31796 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14859277 [patent_doc_number] => 10418374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Vertical memory devices [patent_app_type] => utility [patent_app_number] => 15/398081 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 11475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15398081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11557858 [patent_doc_number] => 20170104103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'THIN-FILM TRANSISTOR, METHOD FOR FABRICATING THIN-FILM TRANSISTOR, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/384622 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 27094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11746653 [patent_doc_number] => 20170200726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/366047 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 22641 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710529 [patent_doc_number] => 20170179028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/350305 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15965 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11959461 [patent_doc_number] => 20170263613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 15/254014 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 136 [patent_figures_cnt] => 136 [patent_no_of_words] => 22452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15254014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15519677 [patent_doc_number] => 10566437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Thin film transistor and array substrate [patent_app_type] => utility [patent_app_number] => 15/241760 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 17515 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11132430 [patent_doc_number] => 20160329405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/212969 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11840266 [patent_doc_number] => 20170221986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'COPOLAR INTEGRATED DIODE' [patent_app_type] => utility [patent_app_number] => 15/211824 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5986 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15211824 [rel_patent_id] =>[rel_patent_doc_number] =>)