Search

Pauline Vu

Examiner (ID: 16349, Phone: (571)272-5265 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2819, 2823
Total Applications
188
Issued Applications
119
Pending Applications
0
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10577077 [patent_doc_number] => 09299727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Array substrate and manufacturing method thereof as well as display panel' [patent_app_type] => utility [patent_app_number] => 14/387885 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14387885 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/387885
Array substrate and manufacturing method thereof as well as display panel Dec 8, 2013 Issued
Array ( [id] => 10418258 [patent_doc_number] => 20150303268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'DIODE AND POWER CONVERSION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/646375 [patent_app_country] => US [patent_app_date] => 2013-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10715 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14646375 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/646375
DIODE AND POWER CONVERSION DEVICE Dec 2, 2013 Abandoned
Array ( [id] => 11551612 [patent_doc_number] => 09620469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Mechanisms for forming post-passivation interconnect structure' [patent_app_type] => utility [patent_app_number] => 14/082997 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082997
Mechanisms for forming post-passivation interconnect structure Nov 17, 2013 Issued
Array ( [id] => 13667299 [patent_doc_number] => 10163828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Semiconductor device and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 14/082849 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6334 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/082849
Semiconductor device and fabricating method thereof Nov 17, 2013 Issued
Array ( [id] => 10544525 [patent_doc_number] => 09269657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Flexible stack packages, electronic systems including the same, and memory cards including the same' [patent_app_type] => utility [patent_app_number] => 14/081020 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14081020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/081020
Flexible stack packages, electronic systems including the same, and memory cards including the same Nov 14, 2013 Issued
Array ( [id] => 9460501 [patent_doc_number] => 20140124927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SEMICONDUCTOR IC PACKAGING METHODS AND STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/074598 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074598 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074598
Semiconductor IC packaging methods and structures Nov 6, 2013 Issued
Array ( [id] => 11551611 [patent_doc_number] => 09620468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Semiconductor packaging structure and method for forming the same' [patent_app_type] => utility [patent_app_number] => 14/074637 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 7537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074637 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074637
Semiconductor packaging structure and method for forming the same Nov 6, 2013 Issued
Array ( [id] => 9460503 [patent_doc_number] => 20140124929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 14/074697 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074697 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074697
Semiconductor device and fabrication method Nov 6, 2013 Issued
Array ( [id] => 9534591 [patent_doc_number] => 20140159237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR ROUTING THE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/068560 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8324 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068560 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068560
Semiconductor package and method for routing the package Oct 30, 2013 Issued
Array ( [id] => 9515371 [patent_doc_number] => 20140151863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/064106 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7621 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064106 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/064106
SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME Oct 24, 2013 Abandoned
Array ( [id] => 9809821 [patent_doc_number] => 20150021767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE WITH PLATED CONDUCTIVE PILLAR COUPLING' [patent_app_type] => utility [patent_app_number] => 14/063829 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14063829 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/063829
SEMICONDUCTOR DEVICE WITH PLATED CONDUCTIVE PILLAR COUPLING Oct 24, 2013 Abandoned
Array ( [id] => 9893305 [patent_doc_number] => 20150048504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'PACKAGE ASSEMBLY FOR CHIP AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/059455 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1708 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059455 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/059455
PACKAGE ASSEMBLY FOR CHIP AND METHOD OF MANUFACTURING SAME Oct 21, 2013 Abandoned
Array ( [id] => 9508840 [patent_doc_number] => 20140145331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/056839 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056839 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056839
MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Oct 16, 2013 Abandoned
Array ( [id] => 13921785 [patent_doc_number] => 10205017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) [patent_app_type] => utility [patent_app_number] => 14/037205 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037205 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037205
Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) Sep 24, 2013 Issued
Array ( [id] => 11214842 [patent_doc_number] => 09443884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Method for manufacturing ESD device, ESD device and display panel' [patent_app_type] => utility [patent_app_number] => 14/368913 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5429 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368913 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368913
Method for manufacturing ESD device, ESD device and display panel Sep 24, 2013 Issued
Array ( [id] => 13921785 [patent_doc_number] => 10205017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) [patent_app_type] => utility [patent_app_number] => 14/037205 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14037205 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/037205
Bottom source NMOS triggered Zener clamp for configuring an ultra-low voltage transient voltage suppressor (TVS) Sep 24, 2013 Issued
Array ( [id] => 10583934 [patent_doc_number] => 09306062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/033892 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/033892
Semiconductor device Sep 22, 2013 Issued
Array ( [id] => 10597501 [patent_doc_number] => 09318597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Layout configurations for integrating schottky contacts into a power transistor device' [patent_app_type] => utility [patent_app_number] => 14/032995 [patent_app_country] => US [patent_app_date] => 2013-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8015 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14032995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/032995
Layout configurations for integrating schottky contacts into a power transistor device Sep 19, 2013 Issued
Array ( [id] => 10903278 [patent_doc_number] => 20140306291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Dual Silicide Process Compatible with Replacement-Metal-Gate' [patent_app_type] => utility [patent_app_number] => 14/010891 [patent_app_country] => US [patent_app_date] => 2013-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12723 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010891
Dual Silicide Process Compatible with Replacement-Metal-Gate Aug 26, 2013 Abandoned
Array ( [id] => 9639254 [patent_doc_number] => 20140217364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Diode Structure and Method for Wire-Last Nanomesh Technologies' [patent_app_type] => utility [patent_app_number] => 13/971974 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6696 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971974 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971974
Diode structure and method for wire-last nanomesh technologies Aug 20, 2013 Issued
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