
Pauline Vu
Examiner (ID: 13658, Phone: (571)272-5265 , Office: P/2823 )
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, 2819 |
| Total Applications | 188 |
| Issued Applications | 119 |
| Pending Applications | 0 |
| Abandoned Applications | 70 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9639254
[patent_doc_number] => 20140217364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-07
[patent_title] => 'Diode Structure and Method for Wire-Last Nanomesh Technologies'
[patent_app_type] => utility
[patent_app_number] => 13/971974
[patent_app_country] => US
[patent_app_date] => 2013-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6696
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971974
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/971974 | Diode structure and method for wire-last nanomesh technologies | Aug 20, 2013 | Issued |
Array
(
[id] => 9613433
[patent_doc_number] => 20140203290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-24
[patent_title] => 'Wire-Last Integration Method and Structure for III-V Nanowire Devices'
[patent_app_type] => utility
[patent_app_number] => 13/967953
[patent_app_country] => US
[patent_app_date] => 2013-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967953
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/967953 | Wire-Last Integration Method and Structure for III-V Nanowire Devices | Aug 14, 2013 | Abandoned |
Array
(
[id] => 9682635
[patent_doc_number] => 20140239398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-28
[patent_title] => 'U-SHAPED SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/968169
[patent_app_country] => US
[patent_app_date] => 2013-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/968169 | U-shaped semiconductor structure | Aug 14, 2013 | Issued |
Array
(
[id] => 9631756
[patent_doc_number] => 20140209864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-07-31
[patent_title] => 'Nanowire Capacitor for Bidirectional Operation'
[patent_app_type] => utility
[patent_app_number] => 13/967807
[patent_app_country] => US
[patent_app_date] => 2013-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/967807 | Nanowire capacitor for bidirectional operation | Aug 14, 2013 | Issued |
Array
(
[id] => 9158801
[patent_doc_number] => 20130307078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-21
[patent_title] => 'SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE'
[patent_app_type] => utility
[patent_app_number] => 13/949606
[patent_app_country] => US
[patent_app_date] => 2013-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/949606 | SILICON ON INSULATOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH AN ISOLATION FORMED AT LOW TEMPERATURE | Jul 23, 2013 | Abandoned |
Array
(
[id] => 9145384
[patent_doc_number] => 20130299907
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/939207
[patent_app_country] => US
[patent_app_date] => 2013-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939207
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/939207 | Semiconductor device and method of manufacturing the same | Jul 10, 2013 | Issued |
Array
(
[id] => 13889361
[patent_doc_number] => 10197227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-05
[patent_title] => Quantum dot containing optical element
[patent_app_type] => utility
[patent_app_number] => 13/924262
[patent_app_country] => US
[patent_app_date] => 2013-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13924262
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/924262 | Quantum dot containing optical element | Jun 20, 2013 | Issued |
Array
(
[id] => 9081553
[patent_doc_number] => 20130267083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'PRODUCING METHOD FOR SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/908538
[patent_app_country] => US
[patent_app_date] => 2013-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 7905
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908538
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/908538 | PRODUCING METHOD FOR SEMICONDUCTOR DEVICE | Jun 2, 2013 | Abandoned |
Array
(
[id] => 9038379
[patent_doc_number] => 20130241017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-19
[patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/886693
[patent_app_country] => US
[patent_app_date] => 2013-05-03
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13886693
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/886693 | SOLID-STATE IMAGE PICKUP DEVICE | May 2, 2013 | Abandoned |
Array
(
[id] => 10903277
[patent_doc_number] => 20140306290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-16
[patent_title] => 'Dual Silicide Process Compatible with Replacement-Metal-Gate'
[patent_app_type] => utility
[patent_app_number] => 13/860743
[patent_app_country] => US
[patent_app_date] => 2013-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 12689
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860743
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/860743 | Dual Silicide Process Compatible with Replacement-Metal-Gate | Apr 10, 2013 | Abandoned |
Array
(
[id] => 9737726
[patent_doc_number] => 20140273444
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS'
[patent_app_type] => utility
[patent_app_number] => 13/836335
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13836335
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/836335 | Multiple-patterned semiconductor device channels | Mar 14, 2013 | Issued |
Array
(
[id] => 9729236
[patent_doc_number] => 20140264943
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/795890 | Multiple-patterned semiconductor device channels | Mar 11, 2013 | Issued |
Array
(
[id] => 9174518
[patent_doc_number] => 20130316503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-28
[patent_title] => 'STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs)'
[patent_app_type] => utility
[patent_app_number] => 13/788689
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/788689 | Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) | Mar 6, 2013 | Issued |
Array
(
[id] => 9869161
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[patent_title] => 'U-shaped semiconductor structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/775917 | U-shaped semiconductor structure | Feb 24, 2013 | Issued |
Array
(
[id] => 8879844
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[patent_title] => 'THIN-FILM TRANSISTOR, METHOD FOR FABRICATING THIN-FILM TRANSISTOR, AND DISPLAY DEVICE'
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Array
(
[id] => 9668050
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[patent_kind] => A1
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[patent_title] => 'Trilayer SIT Process with Transfer Layer for FINFET Patterning'
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Array
(
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Array
(
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[patent_title] => 'ELECTRONIC FUSE HAVING A DAMAGED REGION'
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/745770 | Wire-last integration method and structure for III-V nanowire devices | Jan 18, 2013 | Issued |