Paulinho E. Smith

Array ( [id] => 6233397 [patent_doc_number] => 20100265751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'MULTI-CHIP PACKAGES PROVIDING REDUCED SIGNAL SKEW AND RELATED METHODS OF OPERATION' [patent_app_type] => utility [patent_app_number] => 12/710405 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8526 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265751.pdf [firstpage_image] =>[orig_patent_app_number] => 12710405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8258820 [patent_doc_number] => 08208325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Semiconductor device, semiconductor package and memory repair method' [patent_app_type] => utility [patent_app_number] => 12/694475 [patent_app_country] => US [patent_app_date] => 2010-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12694475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8019831 [patent_doc_number] => 08139424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/654647 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6755 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/139/08139424.pdf [firstpage_image] =>[orig_patent_app_number] => 12654647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7732247 [patent_doc_number] => 08102705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Structure and method for shuffling data within non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/635449 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 15180 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102705.pdf [firstpage_image] =>[orig_patent_app_number] => 12635449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6023180 [patent_doc_number] => 20110051506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'FLEXIBLE MULTI-PULSE SET OPERATION FOR PHASE-CHANGE MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/551553 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4700 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051506.pdf [firstpage_image] =>[orig_patent_app_number] => 12551553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6218977 [patent_doc_number] => 20100054072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'DISTRIBUTED BLOCK RAM' [patent_app_type] => utility [patent_app_number] => 12/549151 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6911 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054072.pdf [firstpage_image] =>[orig_patent_app_number] => 12549151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8387471 [patent_doc_number] => 08264872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Column decoder for non-volatile memory devices, in particular of the phase-change type' [patent_app_type] => utility [patent_app_number] => 12/548241 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5130 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12548241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7999333 [patent_doc_number] => 08081514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Partial speed and full speed programming for non-volatile memory using floating bit lines' [patent_app_type] => utility [patent_app_number] => 12/547449 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081514.pdf [firstpage_image] =>[orig_patent_app_number] => 12547449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8117289 [patent_doc_number] => 08159868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating' [patent_app_type] => utility [patent_app_number] => 12/545623 [patent_app_country] => US [patent_app_date] => 2009-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 15988 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159868.pdf [firstpage_image] =>[orig_patent_app_number] => 12545623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6565312 [patent_doc_number] => 20100046313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/544807 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8658 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046313.pdf [firstpage_image] =>[orig_patent_app_number] => 12544807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7990409 [patent_doc_number] => 08077508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Dynamic multistate memory write driver' [patent_app_type] => utility [patent_app_number] => 12/544189 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/077/08077508.pdf [firstpage_image] =>[orig_patent_app_number] => 12544189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8030843 [patent_doc_number] => 08144511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Selective memory cell program and erase' [patent_app_type] => utility [patent_app_number] => 12/544113 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 15107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144511.pdf [firstpage_image] =>[orig_patent_app_number] => 12544113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8191913 [patent_doc_number] => 08184491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Method for reading memory cell' [patent_app_type] => utility [patent_app_number] => 12/542199 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3424 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/184/08184491.pdf [firstpage_image] =>[orig_patent_app_number] => 12542199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8258811 [patent_doc_number] => 08208317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/461277 [patent_app_country] => US [patent_app_date] => 2009-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7941 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12461277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6309956 [patent_doc_number] => 20100110749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads' [patent_app_type] => utility [patent_app_number] => 12/461141 [patent_app_country] => US [patent_app_date] => 2009-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3469 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110749.pdf [firstpage_image] =>[orig_patent_app_number] => 12461141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8665967 [patent_doc_number] => 08379435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Smart well assisted SRAM read and write' [patent_app_type] => utility [patent_app_number] => 12/507437 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8303 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12507437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8106587 [patent_doc_number] => 08154945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Decoding circuit withstanding high voltage via low-voltage MOS transistor and the implementing method thereof' [patent_app_type] => utility [patent_app_number] => 12/505591 [patent_app_country] => US [patent_app_date] => 2009-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4198 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154945.pdf [firstpage_image] =>[orig_patent_app_number] => 12505591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6133074 [patent_doc_number] => 20110007545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'Non-Volatile Memory Cell Stack with Dual Resistive Elements' [patent_app_type] => utility [patent_app_number] => 12/501751 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007545.pdf [firstpage_image] =>[orig_patent_app_number] => 12501751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6475076 [patent_doc_number] => 20100008175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'BATTERY-LESS CACHE MEMORY MODULE WITH INTEGRATED BACKUP' [patent_app_type] => utility [patent_app_number] => 12/500471 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16982 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008175.pdf [firstpage_image] =>[orig_patent_app_number] => 12500471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8117271 [patent_doc_number] => 08159856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Bipolar select device for resistive sense memory' [patent_app_type] => utility [patent_app_number] => 12/498661 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159856.pdf [firstpage_image] =>[orig_patent_app_number] => 12498661 [rel_patent_id] =>[rel_patent_doc_number] =>)