Search

Peguy Jean Pierre

Examiner (ID: 7372, Phone: (571)272-1803 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2845, 2104, 2819
Total Applications
2975
Issued Applications
2764
Pending Applications
118
Abandoned Applications
117

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20551951 [patent_doc_number] => 12562754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Single-index parity check for polar encoding [patent_app_type] => utility [patent_app_number] => 18/653759 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14978 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653759
Single-index parity check for polar encoding May 1, 2024 Issued
Array ( [id] => 20010883 [patent_doc_number] => 20250149105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/648882 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648882
MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF Apr 28, 2024 Pending
Array ( [id] => 20064284 [patent_doc_number] => 20250202506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 2/3 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647812 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647812 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647812
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 2/3 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20064283 [patent_doc_number] => 20250202505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647792 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647792
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 19758740 [patent_doc_number] => 20250047305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647699 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647699
SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 19515440 [patent_doc_number] => 20240347126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING [patent_app_type] => utility [patent_app_number] => 18/622190 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/622190
Read pass voltage adjustment among multiple erase blocks coupled to a same string Mar 28, 2024 Issued
Array ( [id] => 20283373 [patent_doc_number] => 20250308615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SEQUENTIAL READ TRACKING IN NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/616318 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616318
SEQUENTIAL READ TRACKING IN NON-VOLATILE MEMORY DEVICES Mar 25, 2024 Pending
Array ( [id] => 20624775 [patent_doc_number] => 12592287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Memory, memory system, program method of memory, and electronic apparatus [patent_app_type] => utility [patent_app_number] => 18/614118 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614118
MEMORY, MEMORY SYSTEM, PROGRAM METHOD OF MEMORY, AND ELECTRONIC APPARATUS Mar 21, 2024 Pending
Array ( [id] => 19965430 [patent_doc_number] => 12334954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-17 [patent_title] => Threshold-based min-sum algorithm to lower the error floors of quantized low-density parity-check decoders [patent_app_type] => utility [patent_app_number] => 18/612919 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4186 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612919
Threshold-based min-sum algorithm to lower the error floors of quantized low-density parity-check decoders Mar 20, 2024 Issued
Array ( [id] => 19465603 [patent_doc_number] => 20240319273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => CIRCUIT TESTING [patent_app_type] => utility [patent_app_number] => 18/612710 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612710
CIRCUIT TESTING Mar 20, 2024 Pending
Array ( [id] => 19469173 [patent_doc_number] => 20240322843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DETERMINING BERLEKAMP DISCREPANCY VALUES [patent_app_type] => utility [patent_app_number] => 18/611441 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611441 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611441
DETERMINING BERLEKAMP DISCREPANCY VALUES Mar 19, 2024 Pending
Array ( [id] => 20539120 [patent_doc_number] => 12556202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Electronic device and operation method thereof [patent_app_type] => utility [patent_app_number] => 18/602610 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1683 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/602610
Electronic device and operation method thereof Mar 11, 2024 Issued
Array ( [id] => 20360650 [patent_doc_number] => 12476658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Apparatus and method for designing codes by using polar and algebraic codes [patent_app_type] => utility [patent_app_number] => 18/590531 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590531
Apparatus and method for designing codes by using polar and algebraic codes Feb 27, 2024 Issued
Array ( [id] => 20197433 [patent_doc_number] => 20250274143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => METHOD AND APPARATUS FOR COMPUTING SYNDROMES, ERASURES AND ERRORS MAGNITUDES IN REED-SOLOMON ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/588926 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588926
METHOD AND APPARATUS FOR COMPUTING SYNDROMES, ERASURES AND ERRORS MAGNITUDES IN REED-SOLOMON ERROR CORRECTION Feb 26, 2024 Abandoned
Array ( [id] => 20415715 [patent_doc_number] => 12499001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Efficient performance of error rate detection procedures in a memory system [patent_app_type] => utility [patent_app_number] => 18/581267 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581267
Efficient performance of error rate detection procedures in a memory system Feb 18, 2024 Issued
Array ( [id] => 20168469 [patent_doc_number] => 20250260516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => POLLING IMPROVEMENTS FOR RADIO LINK CONTROL [patent_app_type] => utility [patent_app_number] => 18/440142 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440142
POLLING IMPROVEMENTS FOR RADIO LINK CONTROL Feb 12, 2024 Pending
Array ( [id] => 19305275 [patent_doc_number] => 20240233855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 18/429729 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429729 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429729
METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE Jan 31, 2024 Pending
Array ( [id] => 20530194 [patent_doc_number] => 12548635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Data processing device and method for storing data [patent_app_type] => utility [patent_app_number] => 18/424933 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424933 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424933
Data processing device and method for storing data Jan 28, 2024 Issued
Array ( [id] => 19348929 [patent_doc_number] => 20240257893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 18/424922 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424922
Error detection Jan 28, 2024 Issued
Array ( [id] => 20275363 [patent_doc_number] => 12445150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Low-density parity-check (LDPC) data decoding using iteration-variable accuracy [patent_app_type] => utility [patent_app_number] => 18/418348 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3779 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418348
Low-density parity-check (LDPC) data decoding using iteration-variable accuracy Jan 21, 2024 Issued
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