Search

Peniel M. Gumedzoe

Examiner (ID: 6124, Phone: (571)270-3041 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2891
Total Applications
1595
Issued Applications
1303
Pending Applications
83
Abandoned Applications
248

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14093949 [patent_doc_number] => 10242887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Semiconductor device and method of making embedded wafer level chip scale packages [patent_app_type] => utility [patent_app_number] => 15/674247 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 76 [patent_no_of_words] => 14262 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674247
Semiconductor device and method of making embedded wafer level chip scale packages Aug 9, 2017 Issued
Array ( [id] => 16653379 [patent_doc_number] => 10930572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Method for manufacturing a three dimensional power module [patent_app_type] => utility [patent_app_number] => 16/322766 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3847 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322766
Method for manufacturing a three dimensional power module Jul 27, 2017 Issued
Array ( [id] => 12162686 [patent_doc_number] => 20180033952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/646399 [patent_app_country] => US [patent_app_date] => 2017-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15646399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/646399
Electronic device and method of fabricating the same Jul 10, 2017 Issued
Array ( [id] => 12141116 [patent_doc_number] => 20180019199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYER WITH COPPER MIGRATION STOPPING' [patent_app_type] => utility [patent_app_number] => 15/644403 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644403
SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYER WITH COPPER MIGRATION STOPPING Jul 6, 2017 Abandoned
Array ( [id] => 12129267 [patent_doc_number] => 20180012853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'CHIP PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/643012 [patent_app_country] => US [patent_app_date] => 2017-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5685 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15643012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/643012
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Jul 5, 2017 Abandoned
Array ( [id] => 14429707 [patent_doc_number] => 10319667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Electronic device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/642284 [patent_app_country] => US [patent_app_date] => 2017-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 5295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15642284 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/642284
Electronic device and method of fabricating the same Jul 4, 2017 Issued
Array ( [id] => 15687983 [patent_doc_number] => 20200098655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => ENCLOSURE FOR AN ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 16/619061 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16619061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/619061
Enclosure for an electronic component Jun 29, 2017 Issued
Array ( [id] => 17137711 [patent_doc_number] => 11139278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module [patent_app_type] => utility [patent_app_number] => 16/621700 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 9868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16621700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/621700
Low parasitic inductance power module and double-faced heat-dissipation low parasitic inductance power module Jun 26, 2017 Issued
Array ( [id] => 12516042 [patent_doc_number] => 10002815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Multi-chip package structure manufacturing process and wafer level chip package structure manufacturing process [patent_app_type] => utility [patent_app_number] => 15/628651 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5538 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628651
Multi-chip package structure manufacturing process and wafer level chip package structure manufacturing process Jun 20, 2017 Issued
Array ( [id] => 11967158 [patent_doc_number] => 20170271311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'Package on Package (PoP) Bonding Structures' [patent_app_type] => utility [patent_app_number] => 15/615274 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615274
Package on package (PoP) bonding structures Jun 5, 2017 Issued
Array ( [id] => 13085207 [patent_doc_number] => 10062676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Multilayer chipset structure [patent_app_type] => utility [patent_app_number] => 15/604659 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2337 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 518 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15604659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/604659
Multilayer chipset structure May 24, 2017 Issued
Array ( [id] => 13709189 [patent_doc_number] => 20170365549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/603984 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/603984
Semiconductor device and manufacturing method thereof May 23, 2017 Issued
Array ( [id] => 11952339 [patent_doc_number] => 20170256491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/601305 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601305 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601305
Semiconductor structure and method making the same May 21, 2017 Issued
Array ( [id] => 12195566 [patent_doc_number] => 09899302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Semiconductor package having multi-phase power inverter with internal temperature sensor' [patent_app_type] => utility [patent_app_number] => 15/597359 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597359
Semiconductor package having multi-phase power inverter with internal temperature sensor May 16, 2017 Issued
Array ( [id] => 14267755 [patent_doc_number] => 10283449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Low stress vias [patent_app_type] => utility [patent_app_number] => 15/597699 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 28 [patent_no_of_words] => 13511 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597699
Low stress vias May 16, 2017 Issued
Array ( [id] => 12033756 [patent_doc_number] => 20170323855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'LASER SCRIBE STRUCTURES FOR A WAFER' [patent_app_type] => utility [patent_app_number] => 15/594059 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4280 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594059 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/594059
LASER SCRIBE STRUCTURES FOR A WAFER May 11, 2017 Abandoned
Array ( [id] => 11945997 [patent_doc_number] => 20170250148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/593408 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9457 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593408
Method of manufacturing a semiconductor device May 11, 2017 Issued
Array ( [id] => 11869621 [patent_doc_number] => 20170236906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR WAFER AND METHOD OF INSPECTING SEMICONDUCTOR WAFER' [patent_app_type] => utility [patent_app_number] => 15/586526 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11305 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586526
Semiconductor wafer and method of inspecting semiconductor wafer May 3, 2017 Issued
Array ( [id] => 17638121 [patent_doc_number] => 11348855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Semiconductor component and power module [patent_app_type] => utility [patent_app_number] => 16/097143 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 12932 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16097143 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/097143
Semiconductor component and power module Apr 26, 2017 Issued
Array ( [id] => 12355245 [patent_doc_number] => 09953927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Liner replacements for interconnect openings [patent_app_type] => utility [patent_app_number] => 15/497828 [patent_app_country] => US [patent_app_date] => 2017-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/497828
Liner replacements for interconnect openings Apr 25, 2017 Issued
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