Search

Perry H. Hackley Jr.

Examiner (ID: 17371)

Most Active Art Unit
5332
Art Unit(s)
5332, 5432
Total Applications
486
Issued Applications
0
Pending Applications
486
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17062930 [patent_doc_number] => 11107539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Semiconductor device and its power supply control method [patent_app_type] => utility [patent_app_number] => 16/702167 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6780 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702167
Semiconductor device and its power supply control method Dec 2, 2019 Issued
Array ( [id] => 15656355 [patent_doc_number] => 20200090708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => LAYERED SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/694136 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694136
Layered semiconductor device, and production method therefor Nov 24, 2019 Issued
Array ( [id] => 17252925 [patent_doc_number] => 11188414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/692318 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 20312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692318
Memory system Nov 21, 2019 Issued
Array ( [id] => 16707428 [patent_doc_number] => 10957370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Integration of epitaxially grown channel selector with two terminal resistive switching memory element [patent_app_type] => utility [patent_app_number] => 16/685873 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 8981 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685873 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685873
Integration of epitaxially grown channel selector with two terminal resistive switching memory element Nov 14, 2019 Issued
Array ( [id] => 15984317 [patent_doc_number] => 10672494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Systems and methods to test a memory device [patent_app_type] => utility [patent_app_number] => 16/681703 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681703
Systems and methods to test a memory device Nov 11, 2019 Issued
Array ( [id] => 16264309 [patent_doc_number] => 10755750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Power management integrated circuit load switch driver with dynamic biasing [patent_app_type] => utility [patent_app_number] => 16/661904 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661904
Power management integrated circuit load switch driver with dynamic biasing Oct 22, 2019 Issued
Array ( [id] => 16896062 [patent_doc_number] => 11037623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/597512 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4230 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597512 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597512
Semiconductor memory device Oct 8, 2019 Issued
Array ( [id] => 16424824 [patent_doc_number] => 20200350022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/594760 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594760 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/594760
Storage device and method of operating the same Oct 6, 2019 Issued
Array ( [id] => 16440137 [patent_doc_number] => 20200357464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => ELECTRONIC DEVICE, MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/594866 [patent_app_country] => US [patent_app_date] => 2019-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16594866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/594866
Electronic device, memory device, and method of operating memory device Oct 6, 2019 Issued
Array ( [id] => 16609047 [patent_doc_number] => 10910060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Select line voltage waveform real-time monitor for non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/568986 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 20724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568986 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568986
Select line voltage waveform real-time monitor for non-volatile memory Sep 11, 2019 Issued
Array ( [id] => 16272012 [patent_doc_number] => 20200273500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/568662 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568662
Semiconductor memory device Sep 11, 2019 Issued
Array ( [id] => 16715347 [patent_doc_number] => 20210082494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => CIRCUIT FOR REDUCING VOLTAGE DEGRADATION CAUSED BY PARASITIC RESISTANCE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/568500 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568500
Circuit for reducing voltage degradation caused by parasitic resistance in a memory device Sep 11, 2019 Issued
Array ( [id] => 17877724 [patent_doc_number] => 11449741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Testing circuitry and methods for analog neural memory in artificial neural network [patent_app_type] => utility [patent_app_number] => 16/569647 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 45 [patent_no_of_words] => 15526 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569647 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569647
Testing circuitry and methods for analog neural memory in artificial neural network Sep 11, 2019 Issued
Array ( [id] => 16677032 [patent_doc_number] => 20210065798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => FULLY ASSOCIATIVE CACHE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/555956 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555956 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555956
Fully associative cache management Aug 28, 2019 Issued
Array ( [id] => 16845748 [patent_doc_number] => 11017842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Copy data in a memory system with artificial intelligence mode [patent_app_type] => utility [patent_app_number] => 16/554924 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554924
Copy data in a memory system with artificial intelligence mode Aug 28, 2019 Issued
Array ( [id] => 16521416 [patent_doc_number] => 10872639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Recovery of memory from asynchronous power loss [patent_app_type] => utility [patent_app_number] => 16/555508 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555508
Recovery of memory from asynchronous power loss Aug 28, 2019 Issued
Array ( [id] => 16668226 [patent_doc_number] => 10937479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Integration of epitaxially grown channel selector with MRAM device [patent_app_type] => utility [patent_app_number] => 16/555150 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 8480 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555150
Integration of epitaxially grown channel selector with MRAM device Aug 28, 2019 Issued
Array ( [id] => 16677044 [patent_doc_number] => 20210065810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => ERASING MEMORY [patent_app_type] => utility [patent_app_number] => 16/555050 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555050
Erasing memory Aug 28, 2019 Issued
Array ( [id] => 16386251 [patent_doc_number] => 10811092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => RRAM with plurality of 1TnR structures [patent_app_type] => utility [patent_app_number] => 16/542306 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542306
RRAM with plurality of 1TnR structures Aug 15, 2019 Issued
Array ( [id] => 16631385 [patent_doc_number] => 20210050038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => COUNTERING DIGIT LINE COUPLING IN MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/541940 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541940
Countering digit line coupling in memory arrays Aug 14, 2019 Issued
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