Search

Peter A. Szekely

Examiner (ID: 3545)

Most Active Art Unit
1714
Art Unit(s)
1714, 1761, 1796, 1509, 1766, 2754, 1511
Total Applications
3111
Issued Applications
2334
Pending Applications
106
Abandoned Applications
672

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1514595 [patent_doc_number] => 06420278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method for improving the dielectric constant of silicon-based semiconductor materials' [patent_app_type] => B1 [patent_app_number] => 09/096760 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1840 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420278.pdf [firstpage_image] =>[orig_patent_app_number] => 09096760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096760
Method for improving the dielectric constant of silicon-based semiconductor materials Jun 11, 1998 Issued
Array ( [id] => 4154123 [patent_doc_number] => 06107212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method of and apparatus for manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/090910 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3646 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107212.pdf [firstpage_image] =>[orig_patent_app_number] => 090910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090910
Method of and apparatus for manufacturing semiconductor devices Jun 4, 1998 Issued
Array ( [id] => 4188972 [patent_doc_number] => 06153521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Metallized interconnection structure and method of making the same' [patent_app_type] => 1 [patent_app_number] => 9/090380 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2979 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153521.pdf [firstpage_image] =>[orig_patent_app_number] => 090380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090380
Metallized interconnection structure and method of making the same Jun 3, 1998 Issued
Array ( [id] => 4030819 [patent_doc_number] => 05963797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method of manufacturing semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/086527 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2307 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963797.pdf [firstpage_image] =>[orig_patent_app_number] => 086527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086527
Method of manufacturing semiconductor devices May 28, 1998 Issued
Array ( [id] => 4270786 [patent_doc_number] => 06245691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer' [patent_app_type] => 1 [patent_app_number] => 9/086770 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 6372 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245691.pdf [firstpage_image] =>[orig_patent_app_number] => 086770 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086770
Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer May 28, 1998 Issued
Array ( [id] => 4301984 [patent_doc_number] => 06251739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Integrated circuit, components thereof and manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/083100 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251739.pdf [firstpage_image] =>[orig_patent_app_number] => 083100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083100
Integrated circuit, components thereof and manufacturing method May 21, 1998 Issued
Array ( [id] => 3950648 [patent_doc_number] => 05899734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/083440 [patent_app_country] => US [patent_app_date] => 1998-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 4614 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899734.pdf [firstpage_image] =>[orig_patent_app_number] => 083440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083440
Method of fabricating semiconductor device May 21, 1998 Issued
Array ( [id] => 1417047 [patent_doc_number] => 06509283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Thermal oxidation method utilizing atomic oxygen to reduce dangling bonds in silicon dioxide grown on silicon' [patent_app_type] => B1 [patent_app_number] => 09/076960 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1841 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509283.pdf [firstpage_image] =>[orig_patent_app_number] => 09076960 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076960
Thermal oxidation method utilizing atomic oxygen to reduce dangling bonds in silicon dioxide grown on silicon May 12, 1998 Issued
Array ( [id] => 4131618 [patent_doc_number] => 06146985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Low capacitance interconnection' [patent_app_type] => 1 [patent_app_number] => 9/070912 [patent_app_country] => US [patent_app_date] => 1998-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4142 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146985.pdf [firstpage_image] =>[orig_patent_app_number] => 070912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070912
Low capacitance interconnection May 3, 1998 Issued
Array ( [id] => 4050887 [patent_doc_number] => 05943602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method to cure mobile ion contamination in semiconductor processing' [patent_app_type] => 1 [patent_app_number] => 9/071418 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1888 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943602.pdf [firstpage_image] =>[orig_patent_app_number] => 071418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071418
Method to cure mobile ion contamination in semiconductor processing Apr 30, 1998 Issued
Array ( [id] => 4365800 [patent_doc_number] => 06274419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Trench isolation of field effect transistors' [patent_app_type] => 1 [patent_app_number] => 9/067830 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 34 [patent_no_of_words] => 5101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274419.pdf [firstpage_image] =>[orig_patent_app_number] => 067830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/067830
Trench isolation of field effect transistors Apr 27, 1998 Issued
Array ( [id] => 4355344 [patent_doc_number] => 06200911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps using differential plasma power' [patent_app_type] => 1 [patent_app_number] => 9/264990 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 13226 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200911.pdf [firstpage_image] =>[orig_patent_app_number] => 264990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/264990
Method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps using differential plasma power Apr 20, 1998 Issued
Array ( [id] => 3941806 [patent_doc_number] => 05989977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Shallow trench isolation process' [patent_app_type] => 1 [patent_app_number] => 9/063210 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989977.pdf [firstpage_image] =>[orig_patent_app_number] => 063210 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063210
Shallow trench isolation process Apr 19, 1998 Issued
Array ( [id] => 4344817 [patent_doc_number] => 06284654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Chemical vapor deposition process for fabrication of hybrid electrodes' [patent_app_type] => 1 [patent_app_number] => 9/061380 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5001 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284654.pdf [firstpage_image] =>[orig_patent_app_number] => 061380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/061380
Chemical vapor deposition process for fabrication of hybrid electrodes Apr 15, 1998 Issued
Array ( [id] => 4285903 [patent_doc_number] => 06211014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/059417 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2013 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211014.pdf [firstpage_image] =>[orig_patent_app_number] => 059417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059417
Three-dimensional, deep-trench, high-density read-only memory (ROM) and its manufacturing method Apr 13, 1998 Issued
Array ( [id] => 4303230 [patent_doc_number] => 06187683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for final passivation of integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/059740 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187683.pdf [firstpage_image] =>[orig_patent_app_number] => 059740 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059740
Method for final passivation of integrated circuit Apr 13, 1998 Issued
Array ( [id] => 7028105 [patent_doc_number] => 20010014482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'CAPACITORS AND METHODS OF FORMING CAPACITORS' [patent_app_type] => new [patent_app_number] => 09/059057 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1988 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014482.pdf [firstpage_image] =>[orig_patent_app_number] => 09059057 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059057
Capacitors and methods of forming capacitors Apr 9, 1998 Issued
Array ( [id] => 3994483 [patent_doc_number] => 05985771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers' [patent_app_type] => 1 [patent_app_number] => 9/057152 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3419 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985771.pdf [firstpage_image] =>[orig_patent_app_number] => 057152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057152
Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers Apr 6, 1998 Issued
Array ( [id] => 4357602 [patent_doc_number] => 06174810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Copper interconnect structure and method of formation' [patent_app_type] => 1 [patent_app_number] => 9/055510 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3720 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174810.pdf [firstpage_image] =>[orig_patent_app_number] => 055510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055510
Copper interconnect structure and method of formation Apr 5, 1998 Issued
Array ( [id] => 4070077 [patent_doc_number] => 05933750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Method of fabricating a semiconductor device with a thinned substrate' [patent_app_type] => 1 [patent_app_number] => 9/054561 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1678 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933750.pdf [firstpage_image] =>[orig_patent_app_number] => 054561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/054561
Method of fabricating a semiconductor device with a thinned substrate Apr 2, 1998 Issued
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