Search

Peter A. Szekely

Examiner (ID: 3545)

Most Active Art Unit
1714
Art Unit(s)
1714, 1761, 1796, 1509, 1766, 2754, 1511
Total Applications
3111
Issued Applications
2334
Pending Applications
106
Abandoned Applications
672

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6285002 [patent_doc_number] => 20020053715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Trench isolation structure having a curvilinear interface at upper corners of the trench isolation region, and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/986247 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3899 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053715.pdf [firstpage_image] =>[orig_patent_app_number] => 09986247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986247
Trench isolation structure having a curvilinear interface at upper corners of the trench isolation region, and method of manufacturing the same Nov 7, 2001 Abandoned
Array ( [id] => 6870220 [patent_doc_number] => 20030082909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'High-k gate oxides with buffer layers of titanium for MFOS single transistor memory applications' [patent_app_type] => new [patent_app_number] => 10/015817 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082909.pdf [firstpage_image] =>[orig_patent_app_number] => 10015817 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015817
High-k gate oxides with buffer layers of titanium for MFOS single transistor memory applications Oct 29, 2001 Abandoned
Array ( [id] => 6783135 [patent_doc_number] => 20030064582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Mask layer and interconnect structure for dual damascene semiconductor manufacturing' [patent_app_type] => new [patent_app_number] => 09/966157 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20030064582.pdf [firstpage_image] =>[orig_patent_app_number] => 09966157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966157
Mask layer and interconnect structure for dual damascene semiconductor manufacturing Sep 27, 2001 Abandoned
Array ( [id] => 6720948 [patent_doc_number] => 20030054637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method for forming silicide' [patent_app_type] => new [patent_app_number] => 09/956117 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2245 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054637.pdf [firstpage_image] =>[orig_patent_app_number] => 09956117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956117
Method for forming silicide Sep 19, 2001 Abandoned
Array ( [id] => 1336300 [patent_doc_number] => 06593213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Synthesis of layers, coatings or films using electrostatic fields' [patent_app_type] => B2 [patent_app_number] => 09/957207 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 13504 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593213.pdf [firstpage_image] =>[orig_patent_app_number] => 09957207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957207
Synthesis of layers, coatings or films using electrostatic fields Sep 19, 2001 Issued
Array ( [id] => 5874061 [patent_doc_number] => 20020048886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/955599 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15883 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048886.pdf [firstpage_image] =>[orig_patent_app_number] => 09955599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955599
Semiconductor device and method for fabricating the same Sep 18, 2001 Issued
Array ( [id] => 5885828 [patent_doc_number] => 20020011633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Semiconductor memory device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/953497 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10429 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011633.pdf [firstpage_image] =>[orig_patent_app_number] => 09953497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953497
Semiconductor memory device and method of manufacturing the same Sep 13, 2001 Issued
Array ( [id] => 6720927 [patent_doc_number] => 20030054616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Electronic devices and methods of manufacture' [patent_app_type] => new [patent_app_number] => 09/943237 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6421 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054616.pdf [firstpage_image] =>[orig_patent_app_number] => 09943237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943237
Electronic devices and methods of manufacture Aug 28, 2001 Abandoned
Array ( [id] => 6209421 [patent_doc_number] => 20020072227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method for improving barrier properties of refractory metals/metal nitrides with a safer alternative to silane' [patent_app_type] => new [patent_app_number] => 09/938207 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2050 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072227.pdf [firstpage_image] =>[orig_patent_app_number] => 09938207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938207
Method for improving barrier properties of refractory metals/metal nitrides with a safer alternative to silane Aug 22, 2001 Abandoned
Array ( [id] => 6690939 [patent_doc_number] => 20030038371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'METHOD OF FORMING A METALLIC INTERCONNECT STRUCTURE WITH A METALLIC SPACER' [patent_app_type] => new [patent_app_number] => 09/933947 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1996 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038371.pdf [firstpage_image] =>[orig_patent_app_number] => 09933947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933947
METHOD OF FORMING A METALLIC INTERCONNECT STRUCTURE WITH A METALLIC SPACER Aug 21, 2001 Abandoned
Array ( [id] => 6692733 [patent_doc_number] => 20030040165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method for rounding bottom corner in LOCOS process by using high density plasma poly etcher' [patent_app_type] => new [patent_app_number] => 09/934727 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040165.pdf [firstpage_image] =>[orig_patent_app_number] => 09934727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934727
Method for rounding bottom corner in LOCOS process by using high density plasma poly etcher Aug 21, 2001 Abandoned
Array ( [id] => 6123332 [patent_doc_number] => 20020074581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Feram cell with internal oxygen source and method of oxygen release' [patent_app_type] => new [patent_app_number] => 09/927694 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4112 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074581.pdf [firstpage_image] =>[orig_patent_app_number] => 09927694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927694
Feram cell with internal oxygen source and method of oxygen release Aug 9, 2001 Issued
Array ( [id] => 1528034 [patent_doc_number] => 06479337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Semiconductor device including a charge-dispersing region and fabricating method thereof' [patent_app_type] => B2 [patent_app_number] => 09/911180 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3162 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479337.pdf [firstpage_image] =>[orig_patent_app_number] => 09911180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911180
Semiconductor device including a charge-dispersing region and fabricating method thereof Jul 22, 2001 Issued
Array ( [id] => 1113035 [patent_doc_number] => 06803326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Porous silicon oxycarbide integrated circuit insulator' [patent_app_type] => B2 [patent_app_number] => 09/909532 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3144 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803326.pdf [firstpage_image] =>[orig_patent_app_number] => 09909532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909532
Porous silicon oxycarbide integrated circuit insulator Jul 19, 2001 Issued
Array ( [id] => 5936181 [patent_doc_number] => 20020061635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Solution for chemical mechanical polishing and method of manufacturing copper metal interconnection layer using the same' [patent_app_type] => new [patent_app_number] => 09/899627 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2601 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20020061635.pdf [firstpage_image] =>[orig_patent_app_number] => 09899627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899627
Solution for chemical mechanical polishing and method of manufacturing copper metal interconnection layer using the same Jul 4, 2001 Abandoned
Array ( [id] => 1595471 [patent_doc_number] => 06492221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'DRAM cell arrangement' [patent_app_type] => B1 [patent_app_number] => 09/806427 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8511 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492221.pdf [firstpage_image] =>[orig_patent_app_number] => 09806427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806427
DRAM cell arrangement Jul 2, 2001 Issued
Array ( [id] => 1372015 [patent_doc_number] => 06562712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Multi-step planarizing method for forming a patterned thermally extrudable material layer' [patent_app_type] => B2 [patent_app_number] => 09/898597 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5675 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562712.pdf [firstpage_image] =>[orig_patent_app_number] => 09898597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898597
Multi-step planarizing method for forming a patterned thermally extrudable material layer Jul 2, 2001 Issued
Array ( [id] => 6651379 [patent_doc_number] => 20030008493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Interconnect structure manufacturing' [patent_app_type] => new [patent_app_number] => 09/897637 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008493.pdf [firstpage_image] =>[orig_patent_app_number] => 09897637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897637
Interconnect structure manufacturing Jul 2, 2001 Abandoned
Array ( [id] => 6755842 [patent_doc_number] => 20030003619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Microfluidic structures in a semiconductor substrate and method and apparatus for rapid prototyping and fabrication of same' [patent_app_type] => new [patent_app_number] => 09/895127 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2710 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003619.pdf [firstpage_image] =>[orig_patent_app_number] => 09895127 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895127
Method and apparatus for fabrication of passivated microfluidic structures in semiconductor substrates Jun 28, 2001 Issued
Array ( [id] => 6530447 [patent_doc_number] => 20020192914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas' [patent_app_type] => new [patent_app_number] => 09/882367 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4759 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192914.pdf [firstpage_image] =>[orig_patent_app_number] => 09882367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882367
CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas Jun 14, 2001 Abandoned
Menu