Search

Peter Bradford

Examiner (ID: 19022, Phone: (571)270-1596 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2895
Total Applications
886
Issued Applications
646
Pending Applications
99
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16099033 [patent_doc_number] => 20200203503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICCE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 16/747765 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747765
Method of forming a seed area and growing a heteroepitaxial layer on the seed area Jan 20, 2020 Issued
Array ( [id] => 17700371 [patent_doc_number] => 11374106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Method of making heteroepitaxial structures and device formed by the method [patent_app_type] => utility [patent_app_number] => 16/748327 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 6197 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748327
Method of making heteroepitaxial structures and device formed by the method Jan 20, 2020 Issued
Array ( [id] => 16099035 [patent_doc_number] => 20200203504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICCE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 16/747930 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747930 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747930
Semiconductor product comprising a heteroepitaxial layer grown on a seed area of a nanostructured pedestal Jan 20, 2020 Issued
Array ( [id] => 15939631 [patent_doc_number] => 20200161449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICCE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 16/748361 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748361
Method of making heteroepitaxial structures and device formed by the method Jan 20, 2020 Issued
Array ( [id] => 16120351 [patent_doc_number] => 20200212198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 16/746853 [patent_app_country] => US [patent_app_date] => 2020-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746853
METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD Jan 17, 2020 Abandoned
Array ( [id] => 16966347 [patent_doc_number] => 20210217846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => REDUCTION OF DRAIN LEAKAGE IN NANOSHEET DEVICE [patent_app_type] => utility [patent_app_number] => 16/743256 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743256
Reduction of drain leakage in nanosheet device Jan 14, 2020 Issued
Array ( [id] => 15905993 [patent_doc_number] => 20200152517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => JUNCTION FORMATION IN THICK-OXIDE AND THIN-OXIDE VERTICAL FETS ON THE SAME CHIP [patent_app_type] => utility [patent_app_number] => 16/743216 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5945 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743216
Junction formation in thick-oxide and thin-oxide vertical FETs on the same chip Jan 14, 2020 Issued
Array ( [id] => 15905973 [patent_doc_number] => 20200152507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => INTEGRATED CIRCUIT WITH CONDUCTIVE LINE HAVING LINE-ENDS [patent_app_type] => utility [patent_app_number] => 16/741366 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741366
Integrated circuit with conductive line having line-ends Jan 12, 2020 Issued
Array ( [id] => 16226472 [patent_doc_number] => 20200251589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/739431 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739431
Semiconductor device and fabrication method thereof Jan 9, 2020 Issued
Array ( [id] => 16944421 [patent_doc_number] => 11056674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Organic light-emitting display device including protective layer having edges over pixel-defining layer [patent_app_type] => utility [patent_app_number] => 16/736627 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11736 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736627 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736627
Organic light-emitting display device including protective layer having edges over pixel-defining layer Jan 6, 2020 Issued
Array ( [id] => 17517000 [patent_doc_number] => 11296161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 16/962563 [patent_app_country] => US [patent_app_date] => 2019-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962563
Display panel and display device Dec 24, 2019 Issued
Array ( [id] => 17803521 [patent_doc_number] => 11417834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Apparatus for spin injection enhancement and method of making the same [patent_app_type] => utility [patent_app_number] => 16/725855 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 5903 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16725855 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/725855
Apparatus for spin injection enhancement and method of making the same Dec 22, 2019 Issued
Array ( [id] => 17772518 [patent_doc_number] => 11404470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Method of forming deep trench isolation in radiation sensing substrate and image sensor device [patent_app_type] => utility [patent_app_number] => 16/713884 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713884
Method of forming deep trench isolation in radiation sensing substrate and image sensor device Dec 12, 2019 Issued
Array ( [id] => 16645487 [patent_doc_number] => 10923353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/713306 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713306
Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same Dec 12, 2019 Issued
Array ( [id] => 16593937 [patent_doc_number] => 10903214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/710894 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9718 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 955 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710894 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710894
Semiconductor device Dec 10, 2019 Issued
Array ( [id] => 15776237 [patent_doc_number] => 20200119136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => BURIED MIM CAPACITOR STRUCTURE WITH LANDING PADS [patent_app_type] => utility [patent_app_number] => 16/710781 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710781 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710781
Buried MIM capacitor structure with landing pads Dec 10, 2019 Issued
Array ( [id] => 17758236 [patent_doc_number] => 11398535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Electroluminescent display device with bank between same color sub-pixels [patent_app_type] => utility [patent_app_number] => 16/706127 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 16862 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706127
Electroluminescent display device with bank between same color sub-pixels Dec 5, 2019 Issued
Array ( [id] => 15746085 [patent_doc_number] => 20200111932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/705235 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705235 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705235
Light emitting device encapsulated above electrodes Dec 5, 2019 Issued
Array ( [id] => 16636371 [patent_doc_number] => 10914873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Display substrate, panel, and apparatus having irregular edge portions with partially covered pixels [patent_app_type] => utility [patent_app_number] => 16/705113 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705113 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705113
Display substrate, panel, and apparatus having irregular edge portions with partially covered pixels Dec 4, 2019 Issued
Array ( [id] => 16001195 [patent_doc_number] => 20200176468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHODS FOR FORMING MULTILAYER HORIZONTAL NOR-TYPE THIN-FILM MEMORY STRINGS [patent_app_type] => utility [patent_app_number] => 16/703663 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703663
Methods for forming multilayer horizontal NOR-type thin-film memory strings Dec 3, 2019 Issued
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