Search

Peter Bradford

Examiner (ID: 19022, Phone: (571)270-1596 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2895
Total Applications
886
Issued Applications
646
Pending Applications
99
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16774224 [patent_doc_number] => 10985348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Display panel, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 16/233837 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6211 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233837
Display panel, manufacturing method thereof, and display device Dec 26, 2018 Issued
Array ( [id] => 15250647 [patent_doc_number] => 10510853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => FinFET with two fins on STI [patent_app_type] => utility [patent_app_number] => 16/223204 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 2881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223204
FinFET with two fins on STI Dec 17, 2018 Issued
Array ( [id] => 14510323 [patent_doc_number] => 20190198816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => HIGH-APERTURE-RATIO MICRODISPLAY WITH MICROCAVITY STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/223668 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223668
High-aperture-ratio microdisplay with microcavity structure Dec 17, 2018 Issued
Array ( [id] => 16202112 [patent_doc_number] => 10727292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => OLED with buffer layer over emitting layer [patent_app_type] => utility [patent_app_number] => 16/222558 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222558 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222558
OLED with buffer layer over emitting layer Dec 16, 2018 Issued
Array ( [id] => 15388715 [patent_doc_number] => 10535556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Integrated circuit with conductive line having line-ends [patent_app_type] => utility [patent_app_number] => 16/218591 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218591
Integrated circuit with conductive line having line-ends Dec 12, 2018 Issued
Array ( [id] => 17623372 [patent_doc_number] => 11342438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Device with heteroepitaxial structure made using a growth mask [patent_app_type] => utility [patent_app_number] => 16/162787 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5935 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162787
Device with heteroepitaxial structure made using a growth mask Oct 16, 2018 Issued
Array ( [id] => 17623372 [patent_doc_number] => 11342438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Device with heteroepitaxial structure made using a growth mask [patent_app_type] => utility [patent_app_number] => 16/162787 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5935 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162787
Device with heteroepitaxial structure made using a growth mask Oct 16, 2018 Issued
Array ( [id] => 17623372 [patent_doc_number] => 11342438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Device with heteroepitaxial structure made using a growth mask [patent_app_type] => utility [patent_app_number] => 16/162787 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5935 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162787
Device with heteroepitaxial structure made using a growth mask Oct 16, 2018 Issued
Array ( [id] => 17623372 [patent_doc_number] => 11342438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Device with heteroepitaxial structure made using a growth mask [patent_app_type] => utility [patent_app_number] => 16/162787 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 5935 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16162787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/162787
Device with heteroepitaxial structure made using a growth mask Oct 16, 2018 Issued
Array ( [id] => 13909421 [patent_doc_number] => 20190043915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD OF FORMING DEEP TRENCH ISOLATION IN RADIATION SENSING SUBSTRATE AND IMAGE SENSOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/154839 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154839
Method of forming deep trench isolation in radiation sensing substrate and image sensor device Oct 8, 2018 Issued
Array ( [id] => 17236978 [patent_doc_number] => 11180850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Dynamic precursor dosing for atomic layer deposition [patent_app_type] => utility [patent_app_number] => 16/137329 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11372 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137329
Dynamic precursor dosing for atomic layer deposition Sep 19, 2018 Issued
Array ( [id] => 17231115 [patent_doc_number] => 20210357672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/346435 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346435 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346435
DISPLAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE Aug 29, 2018 Abandoned
Array ( [id] => 15427631 [patent_doc_number] => 10546754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/049902 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16049902 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/049902
Semiconductor structure and manufacturing method thereof Jul 30, 2018 Issued
Array ( [id] => 13559255 [patent_doc_number] => 20180331175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => Method of Forming a Vertical Potential Short in a Periphery Region of a III-Nitride Stack for Preventing Lateral Leakage [patent_app_type] => utility [patent_app_number] => 16/031799 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031799
Method of forming a vertical potential short in a periphery region of a III-nitride stack for preventing lateral leakage Jul 9, 2018 Issued
Array ( [id] => 16803356 [patent_doc_number] => 10998310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Fins with wide base in a FINFET [patent_app_type] => utility [patent_app_number] => 16/030166 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030166
Fins with wide base in a FINFET Jul 8, 2018 Issued
Array ( [id] => 14904535 [patent_doc_number] => 20190296033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/030079 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030079
SEMICONDUCTOR MEMORY DEVICE Jul 8, 2018 Abandoned
Array ( [id] => 13799807 [patent_doc_number] => 20190013442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => PACKAGE FOR MOUNTING LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/029766 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029766
Package for mounting light-emitting device Jul 8, 2018 Issued
Array ( [id] => 15352029 [patent_doc_number] => 20200013906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 16/030249 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030249 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030249
Vertical etch heterolithic integrated circuit devices Jul 8, 2018 Issued
Array ( [id] => 15351575 [patent_doc_number] => 20200013679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => ISOLATION TECHNIQUES FOR HIGH-VOLTAGE DEVICE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/030243 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030243 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030243
Isolation techniques for high-voltage device structures Jul 8, 2018 Issued
Array ( [id] => 13799329 [patent_doc_number] => 20190013203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => Low-Temperature Dopant Activation Process Using a Cap Layer, and MOS Devices Including the Cap Layer [patent_app_type] => utility [patent_app_number] => 16/030269 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030269
Low-Temperature Dopant Activation Process Using a Cap Layer, and MOS Devices Including the Cap Layer Jul 8, 2018 Abandoned
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