Search

Peter Bradford

Examiner (ID: 19022, Phone: (571)270-1596 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2895
Total Applications
886
Issued Applications
646
Pending Applications
99
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14230873 [patent_doc_number] => 20190127609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => NANOPARTICLE FILLED BARRIER ADHESIVE COMPOSITIONS [patent_app_type] => utility [patent_app_number] => 16/309812 [patent_app_country] => US [patent_app_date] => 2017-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16309812 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/309812
Nanoparticle filled barrier adhesive compositions Jun 12, 2017 Issued
Array ( [id] => 11952292 [patent_doc_number] => 20170256443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION' [patent_app_type] => utility [patent_app_number] => 15/600228 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 18906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600228 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600228
Microelectronic elements with post-assembly planarization May 18, 2017 Issued
Array ( [id] => 12147760 [patent_doc_number] => 09882022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Method for manufacturing transistor with SiCN/SiOCN multilayer spacer' [patent_app_type] => utility [patent_app_number] => 15/592150 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4520 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592150 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592150
Method for manufacturing transistor with SiCN/SiOCN multilayer spacer May 9, 2017 Issued
Array ( [id] => 11869471 [patent_doc_number] => 20170236756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'UNIFORM DIELECTRIC RECESS DEPTH DURING FIN REVEAL' [patent_app_type] => utility [patent_app_number] => 15/583595 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4984 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583595
Uniform dielectric recess depth during fin reveal Apr 30, 2017 Issued
Array ( [id] => 11869432 [patent_doc_number] => 20170236717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'UNIFORM DIELECTRIC RECESS DEPTH DURING FIN REVEAL' [patent_app_type] => utility [patent_app_number] => 15/583638 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4988 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583638 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583638
Uniform dielectric recess depth during fin reveal Apr 30, 2017 Issued
Array ( [id] => 11746682 [patent_doc_number] => 20170200754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/470535 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10475 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470535 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470535
Solid-state imaging device, manufacturing method of solid-state imaging device and electronic apparatus Mar 26, 2017 Issued
Array ( [id] => 11732992 [patent_doc_number] => 20170194435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'HYBRID ASPECT RATIO TRAPPING' [patent_app_type] => utility [patent_app_number] => 15/467821 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467821 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467821
Hybrid aspect ratio trapping Mar 22, 2017 Issued
Array ( [id] => 13514729 [patent_doc_number] => 20180308907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => PIXEL ARRANGEMENT STRUCTURE, DISPLAY SUBSTRATE, DISPLAY APPARATUS AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 15/578481 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15578481 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/578481
PIXEL ARRANGEMENT STRUCTURE, DISPLAY SUBSTRATE, DISPLAY APPARATUS AND METHOD OF FABRICATION THEREOF Mar 7, 2017 Abandoned
Array ( [id] => 11911427 [patent_doc_number] => 09780251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Semiconductor structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/451202 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8352 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15451202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/451202
Semiconductor structure and manufacturing method thereof Mar 5, 2017 Issued
Array ( [id] => 11712768 [patent_doc_number] => 20170181267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Thermal Interface Solution with Reduced Adhesion Force' [patent_app_type] => utility [patent_app_number] => 15/443946 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3667 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443946
Thermal interface solution with reduced adhesion force Feb 26, 2017 Issued
Array ( [id] => 11675072 [patent_doc_number] => 20170163796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'METHODS, DEVICES, AND SYSTEMS FOR TRANSFERRING AN ONGOING CALL OF A COMMUNICATION DEVICE USING A PORTABLE COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 15/433946 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433946
Methods, devices, and systems for transferring an ongoing call of a communication device using a portable communication device Feb 14, 2017 Issued
Array ( [id] => 12457137 [patent_doc_number] => 09984916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-29 [patent_title] => Uniform dielectric recess depth during fin reveal [patent_app_type] => utility [patent_app_number] => 15/400643 [patent_app_country] => US [patent_app_date] => 2017-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 4928 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400643 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400643
Uniform dielectric recess depth during fin reveal Jan 5, 2017 Issued
Array ( [id] => 18156433 [patent_doc_number] => 11569428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Superconducting qubit device packages [patent_app_type] => utility [patent_app_number] => 16/347097 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 18486 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347097 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347097
Superconducting qubit device packages Dec 26, 2016 Issued
Array ( [id] => 15184833 [patent_doc_number] => 20190363008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND STRUCTURES RESULTING THEREFROM [patent_app_type] => utility [patent_app_number] => 16/347184 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347184 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347184
Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom Dec 22, 2016 Issued
Array ( [id] => 13667029 [patent_doc_number] => 10163689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Integrated circuit with conductive line having line-ends [patent_app_type] => utility [patent_app_number] => 15/384076 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 4116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384076 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384076
Integrated circuit with conductive line having line-ends Dec 18, 2016 Issued
Array ( [id] => 14813047 [patent_doc_number] => 20190273133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => TRANSISTOR SOURCE/DRAIN AMORPHOUS INTERLAYER ARRANGEMENTS [patent_app_type] => utility [patent_app_number] => 16/347110 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16347110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/347110
TRANSISTOR SOURCE/DRAIN AMORPHOUS INTERLAYER ARRANGEMENTS Dec 13, 2016 Abandoned
Array ( [id] => 11502761 [patent_doc_number] => 20170076946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'Fin Field Effect Transistor (FinFET) Device with Controlled End-to-End Critical Dimension and Method for Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/362603 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/362603
Fin field effect transistor (FinFET) device with controlled end-to-end critical dimension and method for forming the same Nov 27, 2016 Issued
Array ( [id] => 11502913 [patent_doc_number] => 20170077098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'STABLE MULTIPLE THRESHOLD VOLTAGE DEVICES ON REPLACEMENT METAL GATE CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 15/361794 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5606 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361794
Stable multiple threshold voltage devices on replacement metal gate CMOS devices Nov 27, 2016 Issued
Array ( [id] => 11495543 [patent_doc_number] => 20170069728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'FIN STRUCTURE FOR A FINFET DEVICE' [patent_app_type] => utility [patent_app_number] => 15/357839 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357839 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357839
FinFET with two fins on STI Nov 20, 2016 Issued
Array ( [id] => 11732982 [patent_doc_number] => 20170194425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/343569 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9538 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/343569
Semiconductor devices including field effect transistors with dummy gates on isolation Nov 3, 2016 Issued
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