Search

Peter Bradford

Examiner (ID: 19022, Phone: (571)270-1596 , Office: P/2897 )

Most Active Art Unit
2897
Art Unit(s)
2897, 2895
Total Applications
886
Issued Applications
646
Pending Applications
99
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19559840 [patent_doc_number] => 20240371632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => METHOD FOR MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR COMPONENT [patent_app_type] => utility [patent_app_number] => 18/573300 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18573300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/573300
METHOD FOR MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR COMPONENT Jun 30, 2022 Pending
Array ( [id] => 17933392 [patent_doc_number] => 20220328518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => METHODS FOR FORMING MULTILAYER HORIZONTAL NOR-TYPE THIN-FILM MEMORY STRINGS [patent_app_type] => utility [patent_app_number] => 17/809535 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809535
Methods for forming multilayer horizontal NOR-type thin-film memory strings Jun 27, 2022 Issued
Array ( [id] => 19342689 [patent_doc_number] => 12052896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Electroluminescent display device with bank between same color sub-pixels [patent_app_type] => utility [patent_app_number] => 17/845586 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 16886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845586
Electroluminescent display device with bank between same color sub-pixels Jun 20, 2022 Issued
Array ( [id] => 19561884 [patent_doc_number] => 20240373676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/031118 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031118 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031118
DISPLAY PANEL AND DISPLAY DEVICE Jun 16, 2022 Pending
Array ( [id] => 19444675 [patent_doc_number] => 12094967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Structures and methods for source-down vertical semiconductor device [patent_app_type] => utility [patent_app_number] => 17/805131 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9781 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805131
Structures and methods for source-down vertical semiconductor device Jun 1, 2022 Issued
Array ( [id] => 17871031 [patent_doc_number] => 20220293768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 17/828849 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828849
METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD May 30, 2022 Abandoned
Array ( [id] => 17855497 [patent_doc_number] => 20220285540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITHOUT PARASITIC CHANNELS [patent_app_type] => utility [patent_app_number] => 17/751849 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751849
Integration of p-channel and n-channel E-FET III-V devices without parasitic channels May 23, 2022 Issued
Array ( [id] => 17855483 [patent_doc_number] => 20220285526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD [patent_app_type] => utility [patent_app_number] => 17/752228 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752228 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752228
METHOD OF MAKING HETEROEPITAXIAL STRUCTURES AND DEVICE FORMED BY THE METHOD May 23, 2022 Pending
Array ( [id] => 17855173 [patent_doc_number] => 20220285216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR DEVICE WITH SELF-ALIGNED VIAS [patent_app_type] => utility [patent_app_number] => 17/750887 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750887
Semiconductor device with self-aligned vias May 22, 2022 Issued
Array ( [id] => 19958500 [patent_doc_number] => 12328931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Hybrid integrated circuit dies and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/748363 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 21 [patent_no_of_words] => 3227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748363
Hybrid integrated circuit dies and methods of forming the same May 18, 2022 Issued
Array ( [id] => 18791179 [patent_doc_number] => 20230380174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MEMORY DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/745903 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745903
Memory device with source line over a bonding pad May 16, 2022 Issued
Array ( [id] => 17811124 [patent_doc_number] => 20220262959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 17/661642 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661642
Vertical etch heterolithic integrated circuit devices May 1, 2022 Issued
Array ( [id] => 19828792 [patent_doc_number] => 12249586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Film structure for bond pad [patent_app_type] => utility [patent_app_number] => 17/729363 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 8309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729363
Film structure for bond pad Apr 25, 2022 Issued
Array ( [id] => 17780199 [patent_doc_number] => 20220246549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => DEVICE CRACK-STOP STRUCTURE TO PREVENT DAMAGE DUE TO DICING CRACK [patent_app_type] => utility [patent_app_number] => 17/725890 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725890 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725890
Device crack-stop structure to prevent damage due to dicing crack Apr 20, 2022 Issued
Array ( [id] => 17917760 [patent_doc_number] => 20220320156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/724746 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724746 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724746
Solid-state imaging device, with transfer transistor gate electrode having trench gate sections Apr 19, 2022 Issued
Array ( [id] => 20532080 [patent_doc_number] => 12550533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Display panel with openings in corners, display device including the display panel and electronic device including the display device [patent_app_type] => utility [patent_app_number] => 17/721791 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 9528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721791
Display panel with openings in corners, display device including the display panel and electronic device including the display device Apr 14, 2022 Issued
Array ( [id] => 20565992 [patent_doc_number] => 12568616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Method for forming memory patterns and wire patterns simultaneously [patent_app_type] => utility [patent_app_number] => 17/721088 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721088
Method for forming memory patterns and wire patterns simultaneously Apr 13, 2022 Issued
Array ( [id] => 18595196 [patent_doc_number] => 11744118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Array substrate, method of fabricating array substrate, display panel, and method of fabricating display panel [patent_app_type] => utility [patent_app_number] => 17/721023 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721023
Array substrate, method of fabricating array substrate, display panel, and method of fabricating display panel Apr 13, 2022 Issued
Array ( [id] => 17949444 [patent_doc_number] => 20220336463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/718561 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718561
SEMICONDUCTOR ELEMENT MEMORY DEVICE Apr 11, 2022 Pending
Array ( [id] => 17754123 [patent_doc_number] => 20220232328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => PIEZOELECTRIC ELEMENT, PIEZOELECTRIC DEVICE, AND MANUFACTURING METHOD OF PIEZOELECTRIC ELEMENT [patent_app_type] => utility [patent_app_number] => 17/716259 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -48 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716259
Piezoelectric accoustic sensor with multiple vibrating areas Apr 7, 2022 Issued
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