Peter J. Macchiarolo

Array ( [id] => 4863921 [patent_doc_number] => 20080142980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => utility [patent_app_number] => 12/036306 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142980.pdf [firstpage_image] =>[orig_patent_app_number] => 12036306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5512131 [patent_doc_number] => 20090212435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'POWER SEMICONDUCTOR DEVICE INCLUDING A DOUBLE METAL CONTACT' [patent_app_type] => utility [patent_app_number] => 12/036718 [patent_app_country] => US [patent_app_date] => 2008-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1731 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212435.pdf [firstpage_image] =>[orig_patent_app_number] => 12036718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4740043 [patent_doc_number] => 20080233696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/071542 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7279 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233696.pdf [firstpage_image] =>[orig_patent_app_number] => 12071542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5389168 [patent_doc_number] => 20090206480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'FABRICATING LOW COST SOLDER BUMPS ON INTEGRATED CIRCUIT WAFERS' [patent_app_type] => utility [patent_app_number] => 12/034308 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2333 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206480.pdf [firstpage_image] =>[orig_patent_app_number] => 12034308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6366575 [patent_doc_number] => 20100314385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'INDUCTION HEATING COOKING CONTAINER' [patent_app_type] => utility [patent_app_number] => 12/449354 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5287 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314385.pdf [firstpage_image] =>[orig_patent_app_number] => 12449354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5425824 [patent_doc_number] => 20090085134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Wafer-level image sensor module, method of manufacturing the same, and camera module' [patent_app_type] => utility [patent_app_number] => 12/007977 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5985 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085134.pdf [firstpage_image] =>[orig_patent_app_number] => 12007977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4715041 [patent_doc_number] => 20080237563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Diode/superionic conductor/polymer memory structure' [patent_app_type] => utility [patent_app_number] => 12/007347 [patent_app_country] => US [patent_app_date] => 2008-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3339 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237563.pdf [firstpage_image] =>[orig_patent_app_number] => 12007347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4893445 [patent_doc_number] => 20080102543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION' [patent_app_type] => utility [patent_app_number] => 11/968686 [patent_app_country] => US [patent_app_date] => 2008-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7551 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20080102543.pdf [firstpage_image] =>[orig_patent_app_number] => 11968686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4676335 [patent_doc_number] => 20080213965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD FOR MANUFACTURING DMOS DEVICE' [patent_app_type] => utility [patent_app_number] => 11/965086 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1502 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20080213965.pdf [firstpage_image] =>[orig_patent_app_number] => 11965086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13598 [patent_doc_number] => 07803655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Method to manufacture a phase change memory' [patent_app_type] => utility [patent_app_number] => 11/983188 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7098 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/803/07803655.pdf [firstpage_image] =>[orig_patent_app_number] => 11983188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4701840 [patent_doc_number] => 20080061362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 11/934805 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7649 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061362.pdf [firstpage_image] =>[orig_patent_app_number] => 11934805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4772006 [patent_doc_number] => 20080057664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'LOW LEAKAGE MIM CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/932551 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7135 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057664.pdf [firstpage_image] =>[orig_patent_app_number] => 11932551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4704655 [patent_doc_number] => 20080064179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'LOW LEAKAGE MIM CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/932677 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7132 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20080064179.pdf [firstpage_image] =>[orig_patent_app_number] => 11932677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4772005 [patent_doc_number] => 20080057663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'LOW LEAKAGE MIM CAPACITOR' [patent_app_type] => utility [patent_app_number] => 11/932512 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7134 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20080057663.pdf [firstpage_image] =>[orig_patent_app_number] => 11932512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4691217 [patent_doc_number] => 20080083987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => utility [patent_app_number] => 11/930185 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20080083987.pdf [firstpage_image] =>[orig_patent_app_number] => 11930185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4731333 [patent_doc_number] => 20080048329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => utility [patent_app_number] => 11/930187 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048329.pdf [firstpage_image] =>[orig_patent_app_number] => 11930187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4731169 [patent_doc_number] => 20080048232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'TRENCH-CAPACITOR DRAM DEVICE AND MANUFACTURE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/927700 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 3575 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048232.pdf [firstpage_image] =>[orig_patent_app_number] => 11927700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4669917 [patent_doc_number] => 20080044977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'High performance system-on-chip using post passivation process' [patent_app_type] => utility [patent_app_number] => 11/877652 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044977.pdf [firstpage_image] =>[orig_patent_app_number] => 11877652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4669916 [patent_doc_number] => 20080044976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'High performance system-on-chip using post passivation process' [patent_app_type] => utility [patent_app_number] => 11/877647 [patent_app_country] => US [patent_app_date] => 2007-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8786 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044976.pdf [firstpage_image] =>[orig_patent_app_number] => 11877647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14431 [patent_doc_number] => 07808048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'System and method for providing a buried thin film resistor having end caps defined by a dielectric mask' [patent_app_type] => utility [patent_app_number] => 11/974647 [patent_app_country] => US [patent_app_date] => 2007-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 5032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/808/07808048.pdf [firstpage_image] =>[orig_patent_app_number] => 11974647 [rel_patent_id] =>[rel_patent_doc_number] =>)