Search

Peter J. Macchiarolo

Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )

Most Active Art Unit
2879
Art Unit(s)
2856, 2875, 2855, 2879
Total Applications
714
Issued Applications
485
Pending Applications
22
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5016270 [patent_doc_number] => 20070259479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Forming phase change memory arrays' [patent_app_type] => utility [patent_app_number] => 11/827223 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4087 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259479.pdf [firstpage_image] =>[orig_patent_app_number] => 11827223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/827223
Forming phase change memory arrays Jul 10, 2007 Abandoned
Array ( [id] => 5199259 [patent_doc_number] => 20070298577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/766162 [patent_app_country] => US [patent_app_date] => 2007-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3189 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298577.pdf [firstpage_image] =>[orig_patent_app_number] => 11766162 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/766162
Method for manufacturing semiconductor device Jun 20, 2007 Issued
Array ( [id] => 4907202 [patent_doc_number] => 20080017968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Stack type semiconductor package and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/812580 [patent_app_country] => US [patent_app_date] => 2007-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3848 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20080017968.pdf [firstpage_image] =>[orig_patent_app_number] => 11812580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/812580
Stack type semiconductor package and method of fabricating the same Jun 19, 2007 Abandoned
Array ( [id] => 5163111 [patent_doc_number] => 20070284692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'DEVICE ISOLATION STRUCTURE INCORPORATED IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/761949 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2768 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20070284692.pdf [firstpage_image] =>[orig_patent_app_number] => 11761949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/761949
DEVICE ISOLATION STRUCTURE INCORPORATED IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME Jun 11, 2007 Abandoned
Array ( [id] => 122674 [patent_doc_number] => 07704830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Split gate memory cell using sidewall spacers' [patent_app_type] => utility [patent_app_number] => 11/759518 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4129 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/704/07704830.pdf [firstpage_image] =>[orig_patent_app_number] => 11759518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/759518
Split gate memory cell using sidewall spacers Jun 6, 2007 Issued
Array ( [id] => 4743281 [patent_doc_number] => 20080087882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'PROCESS FOR MAKING CONTAINED LAYERS AND DEVICES MADE WITH SAME' [patent_app_type] => utility [patent_app_number] => 11/758269 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7116 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20080087882.pdf [firstpage_image] =>[orig_patent_app_number] => 11758269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/758269
PROCESS FOR MAKING CONTAINED LAYERS AND DEVICES MADE WITH SAME Jun 4, 2007 Abandoned
Array ( [id] => 4708041 [patent_doc_number] => 20080296567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'METHOD OF MAKING THIN FILM TRANSISTORS COMPRISING ZINC-OXIDE-BASED SEMICONDUCTOR MATERIALS' [patent_app_type] => utility [patent_app_number] => 11/757549 [patent_app_country] => US [patent_app_date] => 2007-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15494 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296567.pdf [firstpage_image] =>[orig_patent_app_number] => 11757549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/757549
METHOD OF MAKING THIN FILM TRANSISTORS COMPRISING ZINC-OXIDE-BASED SEMICONDUCTOR MATERIALS Jun 3, 2007 Abandoned
Array ( [id] => 32426 [patent_doc_number] => 07790519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/754751 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 43 [patent_no_of_words] => 12039 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790519.pdf [firstpage_image] =>[orig_patent_app_number] => 11754751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754751
Semiconductor device and manufacturing method thereof May 28, 2007 Issued
Array ( [id] => 5028527 [patent_doc_number] => 20070269974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'METHODS FOR FORMING A METAL CONTACT IN A SEMICONDUCTOR DEVICE IN WHICH AN OHMIC LAYER IS FORMED WHILE FORMING A BARRIER METAL LAYER' [patent_app_type] => utility [patent_app_number] => 11/754639 [patent_app_country] => US [patent_app_date] => 2007-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9189 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20070269974.pdf [firstpage_image] =>[orig_patent_app_number] => 11754639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/754639
METHODS FOR FORMING A METAL CONTACT IN A SEMICONDUCTOR DEVICE IN WHICH AN OHMIC LAYER IS FORMED WHILE FORMING A BARRIER METAL LAYER May 28, 2007 Abandoned
Array ( [id] => 91921 [patent_doc_number] => 07732274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'High voltage deep trench capacitor' [patent_app_type] => utility [patent_app_number] => 11/752608 [patent_app_country] => US [patent_app_date] => 2007-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5284 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/732/07732274.pdf [firstpage_image] =>[orig_patent_app_number] => 11752608 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752608
High voltage deep trench capacitor May 22, 2007 Issued
Array ( [id] => 133804 [patent_doc_number] => 07696550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Bipolar switching PCMO capacitor' [patent_app_type] => utility [patent_app_number] => 11/805177 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4111 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696550.pdf [firstpage_image] =>[orig_patent_app_number] => 11805177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/805177
Bipolar switching PCMO capacitor May 21, 2007 Issued
Array ( [id] => 4839928 [patent_doc_number] => 20080280414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Systems and Methods for Fabricating Vertical Bipolar Devices' [patent_app_type] => utility [patent_app_number] => 11/745214 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3616 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20080280414.pdf [firstpage_image] =>[orig_patent_app_number] => 11745214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/745214
Systems and Methods for Fabricating Vertical Bipolar Devices May 6, 2007 Abandoned
Array ( [id] => 4856527 [patent_doc_number] => 20080265377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER' [patent_app_type] => utility [patent_app_number] => 11/741908 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265377.pdf [firstpage_image] =>[orig_patent_app_number] => 11741908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741908
AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER Apr 29, 2007 Abandoned
Array ( [id] => 303543 [patent_doc_number] => 07534680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Bipolar transistor, BiCMOS device, and method for fabricating thereof' [patent_app_type] => utility [patent_app_number] => 11/797071 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 5931 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 538 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534680.pdf [firstpage_image] =>[orig_patent_app_number] => 11797071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797071
Bipolar transistor, BiCMOS device, and method for fabricating thereof Apr 29, 2007 Issued
Array ( [id] => 5165621 [patent_doc_number] => 20070287208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method of Making Light Emitting Device With Multilayer Silicon-Containing Encapsulant' [patent_app_type] => utility [patent_app_number] => 11/741808 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8964 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20070287208.pdf [firstpage_image] =>[orig_patent_app_number] => 11741808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741808
Method of making light emitting device with multilayer silicon-containing encapsulant Apr 29, 2007 Issued
Array ( [id] => 5245123 [patent_doc_number] => 20070241357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'LED packages with mushroom shaped lenses and methods of manufacturing LED light-emitting devices' [patent_app_type] => utility [patent_app_number] => 11/796240 [patent_app_country] => US [patent_app_date] => 2007-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13441 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241357.pdf [firstpage_image] =>[orig_patent_app_number] => 11796240 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/796240
LED packages with mushroom shaped lenses and methods of manufacturing LED light-emitting devices Apr 26, 2007 Issued
Array ( [id] => 5113100 [patent_doc_number] => 20070197015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer' [patent_app_type] => utility [patent_app_number] => 11/787468 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5562 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197015.pdf [firstpage_image] =>[orig_patent_app_number] => 11787468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/787468
Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer Apr 16, 2007 Abandoned
Array ( [id] => 4679891 [patent_doc_number] => 20080246117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'SURFACE PATTERNED TOPOGRAPHY FEATURE SUITABLE FOR PLANARIZATION' [patent_app_type] => utility [patent_app_number] => 11/696829 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20080246117.pdf [firstpage_image] =>[orig_patent_app_number] => 11696829 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696829
Surface patterned topography feature suitable for planarization Apr 4, 2007 Issued
Array ( [id] => 4719539 [patent_doc_number] => 20080242062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'FABRICATION OF DIVERSE STRUCTURES ON A COMMON SUBSTRATE THROUGH THE USE OF NON-SELECTIVE AREA GROWTH TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/694978 [patent_app_country] => US [patent_app_date] => 2007-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3112 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242062.pdf [firstpage_image] =>[orig_patent_app_number] => 11694978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694978
FABRICATION OF DIVERSE STRUCTURES ON A COMMON SUBSTRATE THROUGH THE USE OF NON-SELECTIVE AREA GROWTH TECHNIQUES Mar 30, 2007 Abandoned
Array ( [id] => 4715221 [patent_doc_number] => 20080237743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Integration Scheme for Dual Work Function Metal Gates' [patent_app_type] => utility [patent_app_number] => 11/694662 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6952 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237743.pdf [firstpage_image] =>[orig_patent_app_number] => 11694662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694662
Integration Scheme for Dual Work Function Metal Gates Mar 29, 2007 Abandoned
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