Search

Peter J. Macchiarolo

Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )

Most Active Art Unit
2879
Art Unit(s)
2856, 2875, 2855, 2879
Total Applications
714
Issued Applications
485
Pending Applications
22
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 576342 [patent_doc_number] => 07456061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method to reduce boron penetration in a SiGe bipolar device' [patent_app_type] => utility [patent_app_number] => 11/694021 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2912 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456061.pdf [firstpage_image] =>[orig_patent_app_number] => 11694021 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694021
Method to reduce boron penetration in a SiGe bipolar device Mar 29, 2007 Issued
Array ( [id] => 243256 [patent_doc_number] => 07588990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer' [patent_app_type] => utility [patent_app_number] => 11/692778 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4469 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/588/07588990.pdf [firstpage_image] =>[orig_patent_app_number] => 11692778 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692778
Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer Mar 27, 2007 Issued
Array ( [id] => 4740069 [patent_doc_number] => 20080233722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER' [patent_app_type] => utility [patent_app_number] => 11/690138 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4806 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233722.pdf [firstpage_image] =>[orig_patent_app_number] => 11690138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/690138
METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER Mar 22, 2007 Abandoned
Array ( [id] => 4740065 [patent_doc_number] => 20080233718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Method of Semiconductor Thin Film Crystallization and Semiconductor Device Fabrication' [patent_app_type] => utility [patent_app_number] => 11/689498 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20080233718.pdf [firstpage_image] =>[orig_patent_app_number] => 11689498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689498
Method of Semiconductor Thin Film Crystallization and Semiconductor Device Fabrication Mar 20, 2007 Abandoned
Array ( [id] => 311011 [patent_doc_number] => 07528035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Vertical trench memory cell with insulating ring' [patent_app_type] => utility [patent_app_number] => 11/688562 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4553 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528035.pdf [firstpage_image] =>[orig_patent_app_number] => 11688562 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688562
Vertical trench memory cell with insulating ring Mar 19, 2007 Issued
Array ( [id] => 579009 [patent_doc_number] => 07452769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Semiconductor device including an improved capacitor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/687568 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 8743 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452769.pdf [firstpage_image] =>[orig_patent_app_number] => 11687568 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687568
Semiconductor device including an improved capacitor and method for manufacturing the same Mar 15, 2007 Issued
Array ( [id] => 326501 [patent_doc_number] => 07514272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method of manufacturing ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 11/717791 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 8109 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514272.pdf [firstpage_image] =>[orig_patent_app_number] => 11717791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717791
Method of manufacturing ferroelectric memory device Mar 12, 2007 Issued
Array ( [id] => 8738189 [patent_doc_number] => 08409959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Vertically base-connected bipolar transistor' [patent_app_type] => utility [patent_app_number] => 11/717462 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4392 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11717462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717462
Vertically base-connected bipolar transistor Mar 12, 2007 Issued
Array ( [id] => 4817034 [patent_doc_number] => 20080224293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Method And Apparatus For Fabricating A Plurality Of Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 11/684849 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6135 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224293.pdf [firstpage_image] =>[orig_patent_app_number] => 11684849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684849
Method and apparatus for fabricating a plurality of semiconductor devices Mar 11, 2007 Issued
Array ( [id] => 5259228 [patent_doc_number] => 20070212860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'METHOD FOR CRYSTALLIZING A SEMICONDUCTOR THIN FILM' [patent_app_type] => utility [patent_app_number] => 11/684908 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8893 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20070212860.pdf [firstpage_image] =>[orig_patent_app_number] => 11684908 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684908
METHOD FOR CRYSTALLIZING A SEMICONDUCTOR THIN FILM Mar 11, 2007 Abandoned
Array ( [id] => 5259165 [patent_doc_number] => 20070212797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Method of forming a ferroelectric device' [patent_app_type] => utility [patent_app_number] => 11/715441 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20070212797.pdf [firstpage_image] =>[orig_patent_app_number] => 11715441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/715441
Method of forming a ferroelectric device Mar 7, 2007 Abandoned
Array ( [id] => 352952 [patent_doc_number] => 07491975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Light-emitting device, method for making the same, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/683112 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8409 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/491/07491975.pdf [firstpage_image] =>[orig_patent_app_number] => 11683112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683112
Light-emitting device, method for making the same, and electronic apparatus Mar 6, 2007 Issued
Array ( [id] => 4695546 [patent_doc_number] => 20080217730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/682928 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2282 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20080217730.pdf [firstpage_image] =>[orig_patent_app_number] => 11682928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682928
METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE Mar 6, 2007 Abandoned
Array ( [id] => 5131190 [patent_doc_number] => 20070207587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Integrated Circuit Devices Including a Capacitor and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 11/680148 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6915 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20070207587.pdf [firstpage_image] =>[orig_patent_app_number] => 11680148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680148
Methods of forming integrated circuit devices including a capacitor Feb 27, 2007 Issued
Array ( [id] => 4727421 [patent_doc_number] => 20080206965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY' [patent_app_type] => utility [patent_app_number] => 11/679308 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3547 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206965.pdf [firstpage_image] =>[orig_patent_app_number] => 11679308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679308
STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY Feb 26, 2007 Abandoned
Array ( [id] => 4727399 [patent_doc_number] => 20080206943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'METHOD OF FORMING STRAINED CMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/679132 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4603 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206943.pdf [firstpage_image] =>[orig_patent_app_number] => 11679132 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679132
METHOD OF FORMING STRAINED CMOS TRANSISTOR Feb 25, 2007 Abandoned
Array ( [id] => 4727429 [patent_doc_number] => 20080206973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Process method to optimize fully silicided gate (FUSI) thru PAI implant' [patent_app_type] => utility [patent_app_number] => 11/710769 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5778 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20080206973.pdf [firstpage_image] =>[orig_patent_app_number] => 11710769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710769
Process method to optimize fully silicided gate (FUSI) thru PAI implant Feb 25, 2007 Abandoned
Array ( [id] => 4762732 [patent_doc_number] => 20080173941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/678582 [patent_app_country] => US [patent_app_date] => 2007-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20080173941.pdf [firstpage_image] =>[orig_patent_app_number] => 11678582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678582
ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS Feb 23, 2007 Abandoned
Array ( [id] => 7711988 [patent_doc_number] => 08093070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method for leakage reduction in fabrication of high-density FRAM arrays' [patent_app_type] => utility [patent_app_number] => 11/706722 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6748 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093070.pdf [firstpage_image] =>[orig_patent_app_number] => 11706722 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706722
Method for leakage reduction in fabrication of high-density FRAM arrays Feb 14, 2007 Issued
Array ( [id] => 4810656 [patent_doc_number] => 20080191287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/674660 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3814 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191287.pdf [firstpage_image] =>[orig_patent_app_number] => 11674660 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674660
Method for fabricating strained-silicon CMOS transistor Feb 12, 2007 Issued
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