
Peter J. Macchiarolo
Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )
| Most Active Art Unit | 2879 |
| Art Unit(s) | 2856, 2875, 2855, 2879 |
| Total Applications | 714 |
| Issued Applications | 485 |
| Pending Applications | 22 |
| Abandoned Applications | 212 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5148829
[patent_doc_number] => 20070048889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'METHOD OF FORMING A PIEZORESISTIVE DEVICE CAPABLE OF SELECTING STANDARDS AND METHOD OF FORMING A CIRCUIT LAYOUT CAPABLE OF SELECTING SUB-CIRCUIT LAYOUTS'
[patent_app_type] => utility
[patent_app_number] => 11/164331
[patent_app_country] => US
[patent_app_date] => 2005-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2450
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20070048889.pdf
[firstpage_image] =>[orig_patent_app_number] => 11164331
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/164331 | METHOD OF FORMING A PIEZORESISTIVE DEVICE CAPABLE OF SELECTING STANDARDS AND METHOD OF FORMING A CIRCUIT LAYOUT CAPABLE OF SELECTING SUB-CIRCUIT LAYOUTS | Nov 17, 2005 | Abandoned |
Array
(
[id] => 581833
[patent_doc_number] => 07449379
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/272342
[patent_app_country] => US
[patent_app_date] => 2005-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 67
[patent_no_of_words] => 14563
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/449/07449379.pdf
[firstpage_image] =>[orig_patent_app_number] => 11272342
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/272342 | Semiconductor device and method for fabricating the same | Nov 13, 2005 | Issued |
Array
(
[id] => 5726985
[patent_doc_number] => 20060057745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Novel oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM'
[patent_app_type] => utility
[patent_app_number] => 11/268352
[patent_app_country] => US
[patent_app_date] => 2005-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4452
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20060057745.pdf
[firstpage_image] =>[orig_patent_app_number] => 11268352
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/268352 | Oxidation structure/method to fabricate a high-performance magnetic tunneling junction MRAM | Nov 6, 2005 | Issued |
Array
(
[id] => 923095
[patent_doc_number] => 07319067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-15
[patent_title] => 'Method of simultaneously controlling ADI-AEI CD differences of openings having different sizes and etching process utilizing the same method'
[patent_app_type] => utility
[patent_app_number] => 11/163981
[patent_app_country] => US
[patent_app_date] => 2005-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3016
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/319/07319067.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163981
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163981 | Method of simultaneously controlling ADI-AEI CD differences of openings having different sizes and etching process utilizing the same method | Nov 6, 2005 | Issued |
Array
(
[id] => 5661614
[patent_doc_number] => 20060252210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND WIRE WITH SILICIDE'
[patent_app_type] => utility
[patent_app_number] => 11/163892
[patent_app_country] => US
[patent_app_date] => 2005-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3751
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20060252210.pdf
[firstpage_image] =>[orig_patent_app_number] => 11163892
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/163892 | Method for fabricating semiconductor device and wire with silicide | Nov 2, 2005 | Issued |
Array
(
[id] => 5807783
[patent_doc_number] => 20060094137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Method of manufacturing ceramic LED packages'
[patent_app_type] => utility
[patent_app_number] => 11/260101
[patent_app_country] => US
[patent_app_date] => 2005-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9529
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20060094137.pdf
[firstpage_image] =>[orig_patent_app_number] => 11260101
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/260101 | Method of manufacturing ceramic LED packages | Oct 25, 2005 | Issued |
Array
(
[id] => 5040772
[patent_doc_number] => 20070093054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'Multiple device types including an inverted-T channel transistor and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/257972
[patent_app_country] => US
[patent_app_date] => 2005-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3512
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20070093054.pdf
[firstpage_image] =>[orig_patent_app_number] => 11257972
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/257972 | Multiple device types including an inverted-T channel transistor and method therefor | Oct 24, 2005 | Issued |
Array
(
[id] => 907063
[patent_doc_number] => 07332395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-19
[patent_title] => 'Method of manufacturing a capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/255972
[patent_app_country] => US
[patent_app_date] => 2005-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7157
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/332/07332395.pdf
[firstpage_image] =>[orig_patent_app_number] => 11255972
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/255972 | Method of manufacturing a capacitor | Oct 23, 2005 | Issued |
Array
(
[id] => 4999906
[patent_doc_number] => 20070042540
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-22
[patent_title] => 'Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts'
[patent_app_type] => utility
[patent_app_number] => 11/254261
[patent_app_country] => US
[patent_app_date] => 2005-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20070042540.pdf
[firstpage_image] =>[orig_patent_app_number] => 11254261
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/254261 | Method of forming a capacitor in a semiconductor device without wet etchant damage to the capacitor parts | Oct 19, 2005 | Issued |
Array
(
[id] => 7593323
[patent_doc_number] => 07651877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-26
[patent_title] => 'Two-dimensional image detecting apparatus and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/666008
[patent_app_country] => US
[patent_app_date] => 2005-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 13336
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/651/07651877.pdf
[firstpage_image] =>[orig_patent_app_number] => 11666008
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/666008 | Two-dimensional image detecting apparatus and method for manufacturing the same | Oct 17, 2005 | Issued |
Array
(
[id] => 473923
[patent_doc_number] => 07230264
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-12
[patent_title] => 'Semiconductor transistor having structural elements of differing materials'
[patent_app_type] => utility
[patent_app_number] => 11/247866
[patent_app_country] => US
[patent_app_date] => 2005-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 6104
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/230/07230264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11247866
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/247866 | Semiconductor transistor having structural elements of differing materials | Oct 6, 2005 | Issued |
Array
(
[id] => 4651650
[patent_doc_number] => 20080038906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-14
[patent_title] => 'Method for Producing P-Type Ga2o3 Film and Method for Producing Pn Junction-Type Ga2o3 Film'
[patent_app_type] => utility
[patent_app_number] => 11/664438
[patent_app_country] => US
[patent_app_date] => 2005-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2032
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20080038906.pdf
[firstpage_image] =>[orig_patent_app_number] => 11664438
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/664438 | Method for Producing P-Type Ga2o3 Film and Method for Producing Pn Junction-Type Ga2o3 Film | Sep 29, 2005 | Abandoned |
Array
(
[id] => 4532887
[patent_doc_number] => 07871832
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-18
[patent_title] => 'Generating an integrated circuit identifier'
[patent_app_type] => utility
[patent_app_number] => 11/663219
[patent_app_country] => US
[patent_app_date] => 2005-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3389
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/871/07871832.pdf
[firstpage_image] =>[orig_patent_app_number] => 11663219
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/663219 | Generating an integrated circuit identifier | Sep 22, 2005 | Issued |
Array
(
[id] => 5593781
[patent_doc_number] => 20060157697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'System and method for adjusting a manufacturing condition of an electronic device and method for manufacturing an electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/232851
[patent_app_country] => US
[patent_app_date] => 2005-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 6768
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20060157697.pdf
[firstpage_image] =>[orig_patent_app_number] => 11232851
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232851 | System and method for adjusting a manufacturing condition of an electronic device and method for manufacturing an electronic device | Sep 22, 2005 | Abandoned |
Array
(
[id] => 5637131
[patent_doc_number] => 20060068104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Thin-film formation in semiconductor device fabrication process and film deposition apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/231962
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 17236
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20060068104.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231962
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231962 | Thin-film formation in semiconductor device fabrication process and film deposition apparatus | Sep 21, 2005 | Abandoned |
Array
(
[id] => 5741317
[patent_doc_number] => 20060087040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/233282
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4377
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20060087040.pdf
[firstpage_image] =>[orig_patent_app_number] => 11233282
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/233282 | Semiconductor device and method of manufacturing the same | Sep 21, 2005 | Abandoned |
Array
(
[id] => 5746534
[patent_doc_number] => 20060109464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-25
[patent_title] => 'Method for detecting alignment accuracy'
[patent_app_type] => utility
[patent_app_number] => 11/231825
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2775
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20060109464.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231825
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231825 | Method for detecting alignment accuracy | Sep 21, 2005 | Abandoned |
Array
(
[id] => 5828279
[patent_doc_number] => 20060063308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Method for cleaning semiconductor device having dual damascene structure'
[patent_app_type] => utility
[patent_app_number] => 11/231441
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2179
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20060063308.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231441
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231441 | Method for cleaning semiconductor device having dual damascene structure | Sep 18, 2005 | Abandoned |
Array
(
[id] => 5710610
[patent_doc_number] => 20060051955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Top layers of metal for high performance IC\'s'
[patent_app_type] => utility
[patent_app_number] => 11/230102
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5958
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20060051955.pdf
[firstpage_image] =>[orig_patent_app_number] => 11230102
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230102 | Top layers of metal for high performance IC's | Sep 18, 2005 | Issued |
Array
(
[id] => 5104404
[patent_doc_number] => 20070063279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-22
[patent_title] => 'Insulation layer for silicon-on-insulator wafer'
[patent_app_type] => utility
[patent_app_number] => 11/231002
[patent_app_country] => US
[patent_app_date] => 2005-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4032
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20070063279.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231002
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231002 | Insulation layer for silicon-on-insulator wafer | Sep 15, 2005 | Abandoned |