Search

Peter J. Macchiarolo

Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )

Most Active Art Unit
2879
Art Unit(s)
2856, 2875, 2855, 2879
Total Applications
714
Issued Applications
485
Pending Applications
22
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5057016 [patent_doc_number] => 20070059938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method and system for etching silicon oxide and silicon nitride with high selectivity relative to silicon' [patent_app_type] => utility [patent_app_number] => 11/226452 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059938.pdf [firstpage_image] =>[orig_patent_app_number] => 11226452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226452
Method and system for etching silicon oxide and silicon nitride with high selectivity relative to silicon Sep 14, 2005 Abandoned
Array ( [id] => 390291 [patent_doc_number] => 07300887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers' [patent_app_type] => utility [patent_app_number] => 11/227542 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7575 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/300/07300887.pdf [firstpage_image] =>[orig_patent_app_number] => 11227542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227542
Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers Sep 14, 2005 Issued
Array ( [id] => 800318 [patent_doc_number] => 07425460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Method for implementation of back-illuminated CMOS or CCD imagers' [patent_app_type] => utility [patent_app_number] => 11/226902 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5005 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425460.pdf [firstpage_image] =>[orig_patent_app_number] => 11226902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/226902
Method for implementation of back-illuminated CMOS or CCD imagers Sep 12, 2005 Issued
Array ( [id] => 5056927 [patent_doc_number] => 20070059849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method and system for BARC optimization for high numerical aperture applications' [patent_app_type] => utility [patent_app_number] => 11/224361 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8497 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20070059849.pdf [firstpage_image] =>[orig_patent_app_number] => 11224361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224361
Method and system for BARC optimization for high numerical aperture applications Sep 11, 2005 Abandoned
Array ( [id] => 296006 [patent_doc_number] => 07541276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer' [patent_app_type] => utility [patent_app_number] => 11/223311 [patent_app_country] => US [patent_app_date] => 2005-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5550 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541276.pdf [firstpage_image] =>[orig_patent_app_number] => 11223311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/223311
Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer Sep 8, 2005 Issued
Array ( [id] => 9087729 [patent_doc_number] => 08559163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Reaction vessel for producing capacitor element, production method for capacitor element, capacitor element and capacitor' [patent_app_type] => utility [patent_app_number] => 11/219731 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11219731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219731
Reaction vessel for producing capacitor element, production method for capacitor element, capacitor element and capacitor Sep 6, 2005 Issued
Array ( [id] => 393906 [patent_doc_number] => 07297599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/219752 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 36 [patent_no_of_words] => 4389 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/297/07297599.pdf [firstpage_image] =>[orig_patent_app_number] => 11219752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219752
Method of fabricating semiconductor device Sep 6, 2005 Issued
Array ( [id] => 5183066 [patent_doc_number] => 20070054420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Substrate structure and method for wideband power decoupling' [patent_app_type] => utility [patent_app_number] => 11/220131 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2798 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20070054420.pdf [firstpage_image] =>[orig_patent_app_number] => 11220131 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/220131
Substrate structure and method for wideband power decoupling Sep 5, 2005 Abandoned
Array ( [id] => 5894934 [patent_doc_number] => 20060003473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Semiconductor device having ferroelectric material capacitor and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/218972 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2856 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003473.pdf [firstpage_image] =>[orig_patent_app_number] => 11218972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218972
Semiconductor device having ferroelectric material capacitor and method of making the same Sep 1, 2005 Issued
Array ( [id] => 5148884 [patent_doc_number] => 20070048944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Low voltage trigger and save area electrostatic discharge device' [patent_app_type] => utility [patent_app_number] => 11/215492 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048944.pdf [firstpage_image] =>[orig_patent_app_number] => 11215492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215492
Low voltage trigger and save area electrostatic discharge device Aug 28, 2005 Issued
Array ( [id] => 564558 [patent_doc_number] => 07465589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Multi-state magnetoresistance random access cell with improved memory storage density' [patent_app_type] => utility [patent_app_number] => 11/212321 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4723 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/465/07465589.pdf [firstpage_image] =>[orig_patent_app_number] => 11212321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212321
Multi-state magnetoresistance random access cell with improved memory storage density Aug 24, 2005 Issued
Array ( [id] => 408137 [patent_doc_number] => 07285454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-23 [patent_title] => 'Bipolar transistors with low base resistance for CMOS integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/207461 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6793 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285454.pdf [firstpage_image] =>[orig_patent_app_number] => 11207461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207461
Bipolar transistors with low base resistance for CMOS integrated circuits Aug 18, 2005 Issued
Array ( [id] => 5588824 [patent_doc_number] => 20060038275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Method and apparatus for manufacturing stacked-type semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/200037 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2389 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20060038275.pdf [firstpage_image] =>[orig_patent_app_number] => 11200037 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200037
Method and apparatus for manufacturing stacked-type semiconductor device Aug 9, 2005 Issued
Array ( [id] => 5828257 [patent_doc_number] => 20060063290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Method of fabricating metal-insulator-metal capacitor' [patent_app_type] => utility [patent_app_number] => 11/197881 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063290.pdf [firstpage_image] =>[orig_patent_app_number] => 11197881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197881
Method of fabricating metal-insulator-metal capacitor Aug 4, 2005 Abandoned
Array ( [id] => 5631693 [patent_doc_number] => 20060148163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method of forming gate insulation layers of different characteristics' [patent_app_type] => utility [patent_app_number] => 11/196881 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7846 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148163.pdf [firstpage_image] =>[orig_patent_app_number] => 11196881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196881
Method of forming gate insulation layers of different characteristics Aug 3, 2005 Abandoned
Array ( [id] => 650903 [patent_doc_number] => 07112480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices' [patent_app_type] => utility [patent_app_number] => 11/187472 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 45 [patent_no_of_words] => 3731 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112480.pdf [firstpage_image] =>[orig_patent_app_number] => 11187472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/187472
Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices Jul 21, 2005 Issued
Array ( [id] => 7228636 [patent_doc_number] => 20050269655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'MEMS scanning mirror with trenched surface and tapered comb teeth for reducing inertia and deformation' [patent_app_type] => utility [patent_app_number] => 11/185271 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8458 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269655.pdf [firstpage_image] =>[orig_patent_app_number] => 11185271 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185271
MEMS scanning mirror with trenched surface and tapered comb teeth for reducing inertia and deformation Jul 18, 2005 Issued
Array ( [id] => 5881036 [patent_doc_number] => 20060030119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/184262 [patent_app_country] => US [patent_app_date] => 2005-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5854 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030119.pdf [firstpage_image] =>[orig_patent_app_number] => 11184262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/184262
Method of manufacturing semiconductor device Jul 17, 2005 Abandoned
Array ( [id] => 662642 [patent_doc_number] => 07101747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Dual work function metal gates and methods of forming' [patent_app_type] => utility [patent_app_number] => 11/180288 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2891 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101747.pdf [firstpage_image] =>[orig_patent_app_number] => 11180288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180288
Dual work function metal gates and methods of forming Jul 12, 2005 Issued
Array ( [id] => 7045694 [patent_doc_number] => 20050250289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Control of dopant diffusion from buried layers in bipolar integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/180457 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9062 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250289.pdf [firstpage_image] =>[orig_patent_app_number] => 11180457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180457
Control of dopant diffusion from buried layers in bipolar integrated circuits Jul 12, 2005 Abandoned
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