
Peter J. Macchiarolo
Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )
| Most Active Art Unit | 2879 |
| Art Unit(s) | 2856, 2875, 2855, 2879 |
| Total Applications | 714 |
| Issued Applications | 485 |
| Pending Applications | 22 |
| Abandoned Applications | 212 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5057016
[patent_doc_number] => 20070059938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Method and system for etching silicon oxide and silicon nitride with high selectivity relative to silicon'
[patent_app_type] => utility
[patent_app_number] => 11/226452
[patent_app_country] => US
[patent_app_date] => 2005-09-15
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[pdf_file] => publications/A1/0059/20070059938.pdf
[firstpage_image] =>[orig_patent_app_number] => 11226452
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226452 | Method and system for etching silicon oxide and silicon nitride with high selectivity relative to silicon | Sep 14, 2005 | Abandoned |
Array
(
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[patent_doc_number] => 07300887
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[patent_kind] => B2
[patent_issue_date] => 2007-11-27
[patent_title] => 'Methods of forming metal nitride layers, and methods of forming semiconductor structures having metal nitride layers'
[patent_app_type] => utility
[patent_app_number] => 11/227542
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Array
(
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[patent_doc_number] => 07425460
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[patent_issue_date] => 2008-09-16
[patent_title] => 'Method for implementation of back-illuminated CMOS or CCD imagers'
[patent_app_type] => utility
[patent_app_number] => 11/226902
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226902 | Method for implementation of back-illuminated CMOS or CCD imagers | Sep 12, 2005 | Issued |
Array
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[id] => 5056927
[patent_doc_number] => 20070059849
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[patent_issue_date] => 2007-03-15
[patent_title] => 'Method and system for BARC optimization for high numerical aperture applications'
[patent_app_type] => utility
[patent_app_number] => 11/224361
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[patent_app_date] => 2005-09-12
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Array
(
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[patent_title] => 'Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer'
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[patent_app_number] => 11/223311
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/223311 | Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer | Sep 8, 2005 | Issued |
Array
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[patent_issue_date] => 2013-10-15
[patent_title] => 'Reaction vessel for producing capacitor element, production method for capacitor element, capacitor element and capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/219731
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Array
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[patent_title] => 'Method of fabricating semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/219752 | Method of fabricating semiconductor device | Sep 6, 2005 | Issued |
Array
(
[id] => 5183066
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[patent_title] => 'Substrate structure and method for wideband power decoupling'
[patent_app_type] => utility
[patent_app_number] => 11/220131
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Array
(
[id] => 5894934
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[patent_title] => 'Semiconductor device having ferroelectric material capacitor and method of making the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/218972 | Semiconductor device having ferroelectric material capacitor and method of making the same | Sep 1, 2005 | Issued |
Array
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[patent_title] => 'Low voltage trigger and save area electrostatic discharge device'
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[patent_app_number] => 11/215492
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Array
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[patent_title] => 'Multi-state magnetoresistance random access cell with improved memory storage density'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212321 | Multi-state magnetoresistance random access cell with improved memory storage density | Aug 24, 2005 | Issued |
Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/180288 | Dual work function metal gates and methods of forming | Jul 12, 2005 | Issued |
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