Peter J. Macchiarolo

Array ( [id] => 6944842 [patent_doc_number] => 20050196891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Providing a charge dissipation structure for an electrostatically driven device' [patent_app_type] => utility [patent_app_number] => 11/113782 [patent_app_country] => US [patent_app_date] => 2005-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196891.pdf [firstpage_image] =>[orig_patent_app_number] => 11113782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7050897 [patent_doc_number] => 20050186784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer' [patent_app_type] => utility [patent_app_number] => 11/112356 [patent_app_country] => US [patent_app_date] => 2005-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5559 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186784.pdf [firstpage_image] =>[orig_patent_app_number] => 11112356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 459766 [patent_doc_number] => 07241663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Maskless multiple sheet polysilicon resistor' [patent_app_type] => utility [patent_app_number] => 11/109231 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6554 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/241/07241663.pdf [firstpage_image] =>[orig_patent_app_number] => 11109231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5720839 [patent_doc_number] => 20060073614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Ferroelectric capacitor structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/102921 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3526 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20060073614.pdf [firstpage_image] =>[orig_patent_app_number] => 11102921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 534323 [patent_doc_number] => 07176099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Hetero-junction bipolar transistor and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/100511 [patent_app_country] => US [patent_app_date] => 2005-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5627 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176099.pdf [firstpage_image] =>[orig_patent_app_number] => 11100511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5635959 [patent_doc_number] => 20060066932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Method of selective etching using etch stop layer' [patent_app_type] => utility [patent_app_number] => 11/090773 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8124 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066932.pdf [firstpage_image] =>[orig_patent_app_number] => 11090773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 612280 [patent_doc_number] => 07147674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-12 [patent_title] => 'Pretreated porous electrode and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/087409 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7962 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/147/07147674.pdf [firstpage_image] =>[orig_patent_app_number] => 11087409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7197311 [patent_doc_number] => 20050164492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Method of manufacturing flexible wiring board' [patent_app_type] => utility [patent_app_number] => 11/087211 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 15269 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164492.pdf [firstpage_image] =>[orig_patent_app_number] => 11087211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7197312 [patent_doc_number] => 20050164493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Shared contact for high-density memory cell design' [patent_app_type] => utility [patent_app_number] => 11/087422 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3545 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164493.pdf [firstpage_image] =>[orig_patent_app_number] => 11087422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5694288 [patent_doc_number] => 20060154435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'METHOD OF FABRICATING TRENCH ISOLATION FOR TRENCH-CAPACITOR DRAM DEVICES' [patent_app_type] => utility [patent_app_number] => 10/907101 [patent_app_country] => US [patent_app_date] => 2005-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1280 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154435.pdf [firstpage_image] =>[orig_patent_app_number] => 10907101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7197306 [patent_doc_number] => 20050164491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Bit line contact hole and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/083782 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2223 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164491.pdf [firstpage_image] =>[orig_patent_app_number] => 11083782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 496867 [patent_doc_number] => 07208380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Interface improvement by stress application during oxide growth through use of backside films' [patent_app_type] => utility [patent_app_number] => 11/083912 [patent_app_country] => US [patent_app_date] => 2005-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208380.pdf [firstpage_image] =>[orig_patent_app_number] => 11083912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7197405 [patent_doc_number] => 20050164512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/082292 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2319 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20050164512.pdf [firstpage_image] =>[orig_patent_app_number] => 11082292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 800330 [patent_doc_number] => 07425472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Semiconductor fuses and semiconductor devices containing the same' [patent_app_type] => utility [patent_app_number] => 11/082066 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6398 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425472.pdf [firstpage_image] =>[orig_patent_app_number] => 11082066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 650910 [patent_doc_number] => 07112487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Method for fabricating a stacked capacitor array having a regular arrangement of a plurality of stacked capacitors' [patent_app_type] => utility [patent_app_number] => 11/079131 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3385 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112487.pdf [firstpage_image] =>[orig_patent_app_number] => 11079131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 485399 [patent_doc_number] => 07217592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Method of magnetic field assisted self-assembly' [patent_app_type] => utility [patent_app_number] => 11/077961 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4128 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217592.pdf [firstpage_image] =>[orig_patent_app_number] => 11077961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 620429 [patent_doc_number] => 07141846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Semiconductor storage device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/076882 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3972 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141846.pdf [firstpage_image] =>[orig_patent_app_number] => 11076882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 322519 [patent_doc_number] => 07517751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Substrate treating method' [patent_app_type] => utility [patent_app_number] => 11/076282 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4531 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517751.pdf [firstpage_image] =>[orig_patent_app_number] => 11076282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7170486 [patent_doc_number] => 20050202626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Method for fabricating a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 11/071532 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1776 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20050202626.pdf [firstpage_image] =>[orig_patent_app_number] => 11071532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 508346 [patent_doc_number] => 07198960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Method for fabricating ferroelectric capacitor' [patent_app_type] => utility [patent_app_number] => 11/071461 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 5124 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/198/07198960.pdf [firstpage_image] =>[orig_patent_app_number] => 11071461 [rel_patent_id] =>[rel_patent_doc_number] =>)