Search

Peter J. Macchiarolo

Supervisory Patent Examiner (ID: 6406, Phone: (571)272-2375 , Office: P/2856 )

Most Active Art Unit
2879
Art Unit(s)
2856, 2875, 2855, 2879
Total Applications
714
Issued Applications
485
Pending Applications
22
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7002407 [patent_doc_number] => 20050167720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/068853 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5000 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167720.pdf [firstpage_image] =>[orig_patent_app_number] => 11068853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068853
Semiconductor device and its manufacturing method Mar 1, 2005 Issued
Array ( [id] => 638276 [patent_doc_number] => 07126178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/068848 [patent_app_country] => US [patent_app_date] => 2005-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5028 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126178.pdf [firstpage_image] =>[orig_patent_app_number] => 11068848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068848
Semiconductor device and its manufacturing method Mar 1, 2005 Issued
Array ( [id] => 7039503 [patent_doc_number] => 20050158922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/066253 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13286 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158922.pdf [firstpage_image] =>[orig_patent_app_number] => 11066253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066253
Method of manufacturing a semiconductor device Feb 27, 2005 Issued
Array ( [id] => 7253545 [patent_doc_number] => 20050142788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'MOSFET performance improvement using deformation in SOI structure' [patent_app_type] => utility [patent_app_number] => 11/065061 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2172 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142788.pdf [firstpage_image] =>[orig_patent_app_number] => 11065061 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065061
MOSFET performance improvement using deformation in SOI structure Feb 24, 2005 Issued
Array ( [id] => 7050855 [patent_doc_number] => 20050186742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/065002 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 18576 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186742.pdf [firstpage_image] =>[orig_patent_app_number] => 11065002 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065002
Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same Feb 23, 2005 Abandoned
Array ( [id] => 404624 [patent_doc_number] => 07288453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Method of fabricating analog capacitor using post-treatment technique' [patent_app_type] => utility [patent_app_number] => 11/063942 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4883 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288453.pdf [firstpage_image] =>[orig_patent_app_number] => 11063942 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063942
Method of fabricating analog capacitor using post-treatment technique Feb 22, 2005 Issued
Array ( [id] => 432203 [patent_doc_number] => 07264976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Advance ridge structure for microlens gapless approach' [patent_app_type] => utility [patent_app_number] => 11/064452 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3127 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/264/07264976.pdf [firstpage_image] =>[orig_patent_app_number] => 11064452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064452
Advance ridge structure for microlens gapless approach Feb 22, 2005 Issued
Array ( [id] => 724377 [patent_doc_number] => 07045417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/061531 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045417.pdf [firstpage_image] =>[orig_patent_app_number] => 11061531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061531
Method of manufacturing semiconductor device Feb 21, 2005 Issued
Array ( [id] => 482733 [patent_doc_number] => 07220664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently' [patent_app_type] => utility [patent_app_number] => 11/061731 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2742 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220664.pdf [firstpage_image] =>[orig_patent_app_number] => 11061731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061731
Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently Feb 21, 2005 Issued
Array ( [id] => 322564 [patent_doc_number] => 07517796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Method for patterning submicron pillars' [patent_app_type] => utility [patent_app_number] => 11/061952 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7010 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517796.pdf [firstpage_image] =>[orig_patent_app_number] => 11061952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061952
Method for patterning submicron pillars Feb 16, 2005 Issued
Array ( [id] => 7185528 [patent_doc_number] => 20050191806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Method for fabricating a memory cell' [patent_app_type] => utility [patent_app_number] => 11/055431 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20050191806.pdf [firstpage_image] =>[orig_patent_app_number] => 11055431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055431
Method for fabricating a memory cell Feb 9, 2005 Issued
Array ( [id] => 5736085 [patent_doc_number] => 20060006475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions' [patent_app_type] => utility [patent_app_number] => 11/055504 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2286 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006475.pdf [firstpage_image] =>[orig_patent_app_number] => 11055504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055504
Fabrication of an EEPROM cell with emitter-polysilicon source/drain regions Feb 9, 2005 Issued
Array ( [id] => 740829 [patent_doc_number] => 07029932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Circuit and method for measuring contact resistance' [patent_app_type] => utility [patent_app_number] => 11/052121 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/029/07029932.pdf [firstpage_image] =>[orig_patent_app_number] => 11052121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/052121
Circuit and method for measuring contact resistance Feb 6, 2005 Issued
Array ( [id] => 5645923 [patent_doc_number] => 20060131655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Formation of deep trench airgaps and related applications' [patent_app_type] => utility [patent_app_number] => 11/048642 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131655.pdf [firstpage_image] =>[orig_patent_app_number] => 11048642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048642
Formation of deep trench airgaps and related applications Jan 30, 2005 Issued
Array ( [id] => 7094794 [patent_doc_number] => 20050127437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/045148 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7188 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20050127437.pdf [firstpage_image] =>[orig_patent_app_number] => 11045148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/045148
Semiconductor device and method for fabricating the same Jan 30, 2005 Issued
Array ( [id] => 705413 [patent_doc_number] => 07059859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/038502 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3226 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/059/07059859.pdf [firstpage_image] =>[orig_patent_app_number] => 11038502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038502
Manufacturing method of semiconductor device Jan 20, 2005 Issued
Array ( [id] => 5874515 [patent_doc_number] => 20060166423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Removal spacer formation with carbon film' [patent_app_type] => utility [patent_app_number] => 11/040782 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1461 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166423.pdf [firstpage_image] =>[orig_patent_app_number] => 11040782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040782
Removal spacer formation with carbon film Jan 20, 2005 Abandoned
Array ( [id] => 686574 [patent_doc_number] => 07078285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material' [patent_app_type] => utility [patent_app_number] => 11/040781 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 4094 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078285.pdf [firstpage_image] =>[orig_patent_app_number] => 11040781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040781
SiGe nickel barrier structure employed in a CMOS device to prevent excess diffusion of nickel used in the silicide material Jan 20, 2005 Issued
Array ( [id] => 500000 [patent_doc_number] => 07205164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods' [patent_app_type] => utility [patent_app_number] => 11/039301 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 16618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205164.pdf [firstpage_image] =>[orig_patent_app_number] => 11039301 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039301
Methods for fabricating magnetic cell junctions and a structure resulting and/or used for such methods Jan 18, 2005 Issued
Array ( [id] => 5694340 [patent_doc_number] => 20060154487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'ETCHING PROCESS TO AVOID POLYSILICON NOTCHING' [patent_app_type] => utility [patent_app_number] => 11/033912 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3356 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154487.pdf [firstpage_image] =>[orig_patent_app_number] => 11033912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033912
Etching process to avoid polysilicon notching Jan 10, 2005 Issued
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