Search

Peter M. Albrecht

Examiner (ID: 4457, Phone: (571)272-7813 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
606
Issued Applications
384
Pending Applications
89
Abandoned Applications
146

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20291075 [patent_doc_number] => 20250316318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/040550 [patent_app_country] => US [patent_app_date] => 2025-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19040550 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/040550
MEMORY DEVICE AND OPERATION METHOD THEREOF Jan 28, 2025 Pending
Array ( [id] => 19987599 [patent_doc_number] => 20250125821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => ENCODING METHOD, DECODING METHOD, AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/999078 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18999078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/999078
ENCODING METHOD, DECODING METHOD, AND APPARATUS Dec 22, 2024 Pending
Array ( [id] => 19891974 [patent_doc_number] => 20250117286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => Low-Overhead, Bidirectional Error Checking for a Serial Peripheral Interface [patent_app_type] => utility [patent_app_number] => 18/989086 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/989086
Low-Overhead, Bidirectional Error Checking for a Serial Peripheral Interface Dec 19, 2024 Pending
Array ( [id] => 19891975 [patent_doc_number] => 20250117287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => METHOD FOR PROCESSING MEMORY FAULT AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 18/984543 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984543
METHOD FOR PROCESSING MEMORY FAULT AND RELATED DEVICE Dec 16, 2024 Pending
18/874584 DETECTION AND CORRECTION OF ERRORS USING LIMITED ERROR CORRECTION DATA Dec 11, 2024 Pending
Array ( [id] => 20064286 [patent_doc_number] => 20250202508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => COMPUTER SYSTEM AND METHOD FOR ARITHMETIC DECODING [patent_app_type] => utility [patent_app_number] => 18/977678 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977678
COMPUTER SYSTEM AND METHOD FOR ARITHMETIC DECODING Dec 10, 2024 Pending
Array ( [id] => 19851599 [patent_doc_number] => 20250096950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => POWER CONTROL FOR HYBRID AUTOMATIC REPEAT REQUEST [patent_app_type] => utility [patent_app_number] => 18/970343 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970343
POWER CONTROL FOR HYBRID AUTOMATIC REPEAT REQUEST Dec 4, 2024 Pending
Array ( [id] => 20208612 [patent_doc_number] => 20250278332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => INTEGRATED CIRCUIT AND MEMORY SYSTEM INCLUDING ECC CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/948486 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -43 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948486
INTEGRATED CIRCUIT AND MEMORY SYSTEM INCLUDING ECC CIRCUIT Nov 14, 2024 Pending
Array ( [id] => 19787388 [patent_doc_number] => 20250061067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND RELATED METHODS AND APPARATUSES [patent_app_type] => utility [patent_app_number] => 18/936671 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18936671 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/936671
INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND RELATED METHODS AND APPARATUSES Nov 3, 2024 Pending
Array ( [id] => 20409790 [patent_doc_number] => 20250378899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => MEMORY HAVING LATCH CIRCUIT AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/810519 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810519 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810519
MEMORY HAVING LATCH CIRCUIT AND MEMORY SYSTEM Aug 20, 2024 Pending
Array ( [id] => 20197508 [patent_doc_number] => 20250274218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MULTI-RATE LOW-DENSITY PARITY CHECK (LDPC) CODES [patent_app_type] => utility [patent_app_number] => 18/790358 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790358
MULTI-RATE LOW-DENSITY PARITY CHECK (LDPC) CODES Jul 30, 2024 Pending
Array ( [id] => 20210130 [patent_doc_number] => 20250279850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => SYSTEMS AND METHODS FOR EXTENDED LONG RANGE COMMUNICATION IN WIRELESS LOCAL AREA NETWORKS (WLANS) [patent_app_type] => utility [patent_app_number] => 18/790434 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790434
SYSTEMS AND METHODS FOR EXTENDED LONG RANGE COMMUNICATION IN WIRELESS LOCAL AREA NETWORKS (WLANS) Jul 30, 2024 Pending
Array ( [id] => 19992672 [patent_doc_number] => 20250130894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => DYNAMICALLY ENABLING FOREGROUND SCANS OF MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 18/776314 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776314
DYNAMICALLY ENABLING FOREGROUND SCANS OF MEMORY BLOCKS Jul 17, 2024 Pending
Array ( [id] => 19711288 [patent_doc_number] => 20250021430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => METADATA TRANSFER USING UNASSIGNED CODES OF AN ENCODER [patent_app_type] => utility [patent_app_number] => 18/764003 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764003
METADATA TRANSFER USING UNASSIGNED CODES OF AN ENCODER Jul 2, 2024 Pending
Array ( [id] => 19694989 [patent_doc_number] => 20250013534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => TECHNIQUES FOR DATA PATH ADDRESS PROTECTION [patent_app_type] => utility [patent_app_number] => 18/762327 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762327
TECHNIQUES FOR DATA PATH ADDRESS PROTECTION Jul 1, 2024 Pending
Array ( [id] => 20368279 [patent_doc_number] => 20250358091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => DIE-TO-DIE INTERFACE USING SIMULTANEOUS BIDIRECTIONAL LINKS ON AN INTERPOSER [patent_app_type] => utility [patent_app_number] => 18/668724 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668724 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668724
DIE-TO-DIE INTERFACE USING SIMULTANEOUS BIDIRECTIONAL LINKS ON AN INTERPOSER May 19, 2024 Pending
Array ( [id] => 20296582 [patent_doc_number] => 20250321825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => NON-VOLATILE MEMORY WITH TAIL BIT IDENTIFICATION FOR IN-PLACE ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/635463 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635463
NON-VOLATILE MEMORY WITH TAIL BIT IDENTIFICATION FOR IN-PLACE ERROR CORRECTION Apr 14, 2024 Pending
Array ( [id] => 19466416 [patent_doc_number] => 20240320086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => ERROR DETECTION FOR ENCRYPTION OR DECRYPTION KEYS [patent_app_type] => utility [patent_app_number] => 18/612421 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612421
ERROR DETECTION FOR ENCRYPTION OR DECRYPTION KEYS Mar 20, 2024 Abandoned
Array ( [id] => 19283885 [patent_doc_number] => 20240220361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/608460 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608460
REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE Mar 17, 2024 Pending
Array ( [id] => 19266771 [patent_doc_number] => 20240210472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/597215 [patent_app_country] => US [patent_app_date] => 2024-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597215 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597215
HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE Mar 5, 2024 Pending
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