
Peter M. Albrecht
Examiner (ID: 14218, Phone: (571)272-7813 , Office: P/2811 )
| Most Active Art Unit | 2811 |
| Art Unit(s) | 2811 |
| Total Applications | 612 |
| Issued Applications | 385 |
| Pending Applications | 94 |
| Abandoned Applications | 146 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12850351
[patent_doc_number] => 20180175290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => FORMING NUCLEATION LAYERS IN CORRELATED ELECTRON MATERIAL DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/383926
[patent_app_country] => US
[patent_app_date] => 2016-12-19
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Array
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[patent_doc_number] => 20180174940
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[patent_issue_date] => 2018-06-21
[patent_title] => FINE-FEATURED TRACES FOR INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 15/383858
[patent_app_country] => US
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2017-06-08
[patent_title] => 'THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/371897
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[patent_app_date] => 2016-12-07
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Array
(
[id] => 11694587
[patent_doc_number] => 20170170304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-06-15
[patent_title] => 'BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/370154
[patent_app_country] => US
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Array
(
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[patent_title] => 'REGULATING INTERFACE LAYER FORMATION FOR TWO-TERMINAL MEMORY'
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Array
(
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[patent_title] => Semiconductor device, method of manufacturing a semiconductor device, solid-state imaging device, and electronic apparatus
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Array
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[patent_title] => Ultraviolet light-emitting element
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Array
(
[id] => 12692902
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[patent_kind] => A1
[patent_issue_date] => 2018-05-03
[patent_title] => FABRICATION OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING TOP AIR SPACERS AND A SELF-ALIGNED TOP JUNCTION
[patent_app_type] => utility
[patent_app_number] => 15/336309
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/336309 | Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction | Oct 26, 2016 | Issued |
Array
(
[id] => 13514847
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Array
(
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[patent_title] => Self-aligned nanostructures for semiconductor devices
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Array
(
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[patent_title] => Gate oxide structure and method for fabricating the same
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Array
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Array
(
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Array
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Array
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Array
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