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Peter M. Bythrow

Examiner (ID: 2820, Phone: (571)270-1468 , Office: P/3648 )

Most Active Art Unit
3648
Art Unit(s)
3648, 3646, 3662, 4182
Total Applications
1488
Issued Applications
1319
Pending Applications
70
Abandoned Applications
138

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4244028 [patent_doc_number] => 06081022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Clock distribution network with efficient shielding' [patent_app_type] => 1 [patent_app_number] => 9/317787 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3124 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081022.pdf [firstpage_image] =>[orig_patent_app_number] => 317787 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317787
Clock distribution network with efficient shielding May 23, 1999 Issued
Array ( [id] => 4101376 [patent_doc_number] => 06097049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'DRAM cell arrangement' [patent_app_type] => 1 [patent_app_number] => 9/272077 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8632 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097049.pdf [firstpage_image] =>[orig_patent_app_number] => 272077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272077
DRAM cell arrangement Mar 17, 1999 Issued
Array ( [id] => 4215300 [patent_doc_number] => 06087226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Methods of forming capacitors including electrodes with hemispherical grained silicon layers on sidewalls thereof and related structures' [patent_app_type] => 1 [patent_app_number] => 9/048501 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2553 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087226.pdf [firstpage_image] =>[orig_patent_app_number] => 048501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048501
Methods of forming capacitors including electrodes with hemispherical grained silicon layers on sidewalls thereof and related structures Mar 25, 1998 Issued
Array ( [id] => 4070398 [patent_doc_number] => 06008512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Semiconductor device with increased maximum terminal voltage' [patent_app_type] => 1 [patent_app_number] => 8/053243 [patent_app_country] => US [patent_app_date] => 1993-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1881 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008512.pdf [firstpage_image] =>[orig_patent_app_number] => 053243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/053243
Semiconductor device with increased maximum terminal voltage Apr 27, 1993 Issued
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