Search

Peter M. Poon

Supervisory Patent Examiner (ID: 9670, Phone: (571)272-6891 , Office: P/3643 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3103, 3643, 3644
Total Applications
884
Issued Applications
571
Pending Applications
66
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5903562 [patent_doc_number] => 20060046445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method' [patent_app_type] => utility [patent_app_number] => 11/258037 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4748 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046445.pdf [firstpage_image] =>[orig_patent_app_number] => 11258037 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258037
Conductive line for a semiconductor device using a carbon nanotube including a memory thin film and semiconductor device manufactured Oct 25, 2005 Issued
Array ( [id] => 408159 [patent_doc_number] => 07285476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same' [patent_app_type] => utility [patent_app_number] => 11/242017 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 23030 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285476.pdf [firstpage_image] =>[orig_patent_app_number] => 11242017 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242017
Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same Oct 3, 2005 Issued
Array ( [id] => 6931348 [patent_doc_number] => 20050282383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Systems for forming insulative coatings for via holes in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/212226 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282383.pdf [firstpage_image] =>[orig_patent_app_number] => 11212226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212226
Systems for forming insulative coatings for via holes in semiconductor devices Aug 24, 2005 Issued
Array ( [id] => 522625 [patent_doc_number] => 07190074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Reconstructed semiconductor wafers including alignment droplets contacting alignment vias' [patent_app_type] => utility [patent_app_number] => 11/196584 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5445 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190074.pdf [firstpage_image] =>[orig_patent_app_number] => 11196584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196584
Reconstructed semiconductor wafers including alignment droplets contacting alignment vias Aug 1, 2005 Issued
Array ( [id] => 5242379 [patent_doc_number] => 20070020874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'METHOD FOR CONTROLLING DISLOCATION POSITIONS IN SILICON GERMANIUM BUFFER LAYERS' [patent_app_type] => utility [patent_app_number] => 11/187444 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6429 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020874.pdf [firstpage_image] =>[orig_patent_app_number] => 11187444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/187444
Method for controlling dislocation positions in silicon germanium buffer layers Jul 21, 2005 Issued
Array ( [id] => 5771149 [patent_doc_number] => 20050266682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Methods and apparatus for forming barrier layers in high aspect ratio vias' [patent_app_type] => utility [patent_app_number] => 11/185248 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14851 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20050266682.pdf [firstpage_image] =>[orig_patent_app_number] => 11185248 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/185248
Methods and apparatus for forming barrier layers in high aspect ratio vias Jul 18, 2005 Abandoned
Array ( [id] => 5628863 [patent_doc_number] => 20060145331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Printed circuit board including embedded chips and method of fabricating the same using plating' [patent_app_type] => utility [patent_app_number] => 11/179864 [patent_app_country] => US [patent_app_date] => 2005-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3997 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145331.pdf [firstpage_image] =>[orig_patent_app_number] => 11179864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/179864
Printed circuit board including embedded chips and method of fabricating the same using plating Jul 10, 2005 Issued
Array ( [id] => 620437 [patent_doc_number] => 07141854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Double-gated silicon-on-insulator (SOI) transistors with corner rounding' [patent_app_type] => utility [patent_app_number] => 11/174857 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2857 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141854.pdf [firstpage_image] =>[orig_patent_app_number] => 11174857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/174857
Double-gated silicon-on-insulator (SOI) transistors with corner rounding Jul 4, 2005 Issued
Array ( [id] => 5208158 [patent_doc_number] => 20070246742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method of Manufacturing a Strained Semiconductor Layer, Method of Manufacturing a Semiconductor Device and Semiconductor Substrate Suitable for Use in Such a Method' [patent_app_type] => utility [patent_app_number] => 11/629684 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3358 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20070246742.pdf [firstpage_image] =>[orig_patent_app_number] => 11629684 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/629684
Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method including having a thin delta profile layer of germanium close to the bottom of the strained layer Jun 6, 2005 Issued
Array ( [id] => 496646 [patent_doc_number] => 07208332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Methods for preserving strained semiconductor substrate layers during CMOS processing' [patent_app_type] => utility [patent_app_number] => 11/132856 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6294 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208332.pdf [firstpage_image] =>[orig_patent_app_number] => 11132856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/132856
Methods for preserving strained semiconductor substrate layers during CMOS processing May 18, 2005 Issued
Array ( [id] => 397954 [patent_doc_number] => 07294923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Metallization scheme including a low modulus structure' [patent_app_type] => utility [patent_app_number] => 11/121413 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294923.pdf [firstpage_image] =>[orig_patent_app_number] => 11121413 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/121413
Metallization scheme including a low modulus structure May 3, 2005 Issued
Array ( [id] => 4816787 [patent_doc_number] => 20080224046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Method of Treating Non-Refrigerated, Spectrally-Selective Lead Selenide Infrared Detectors' [patent_app_type] => utility [patent_app_number] => 11/632223 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3275 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20080224046.pdf [firstpage_image] =>[orig_patent_app_number] => 11632223 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/632223
Method of Treating Non-Refrigerated, Spectrally-Selective Lead Selenide Infrared Detectors Apr 28, 2005 Abandoned
Array ( [id] => 609523 [patent_doc_number] => 07151053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Method of depositing dielectric materials including oxygen-doped silicon carbide in damascene applications' [patent_app_type] => utility [patent_app_number] => 11/118678 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 8050 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151053.pdf [firstpage_image] =>[orig_patent_app_number] => 11118678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/118678
Method of depositing dielectric materials including oxygen-doped silicon carbide in damascene applications Apr 27, 2005 Issued
Array ( [id] => 5810510 [patent_doc_number] => 20060081618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Non-thermal annealing of doped semiconductor material' [patent_app_type] => utility [patent_app_number] => 11/112643 [patent_app_country] => US [patent_app_date] => 2005-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1597 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081618.pdf [firstpage_image] =>[orig_patent_app_number] => 11112643 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/112643
Non-thermal annealing with electromagnetic radiation in the terahertz range of doped semiconductor material Apr 21, 2005 Issued
Array ( [id] => 7111232 [patent_doc_number] => 20050208688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Surface emitting semiconductor laser and process for producing the same' [patent_app_type] => utility [patent_app_number] => 11/109753 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7930 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208688.pdf [firstpage_image] =>[orig_patent_app_number] => 11109753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/109753
Surface emitting semiconductor laser and process for producing the same including forming an insulating layer on the lower reflector Apr 19, 2005 Issued
Array ( [id] => 7136905 [patent_doc_number] => 20050181582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Contact structure of wiring and a method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/107889 [patent_app_country] => US [patent_app_date] => 2005-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9918 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181582.pdf [firstpage_image] =>[orig_patent_app_number] => 11107889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/107889
Contact structure of wiring and a method for manufacturing the same Apr 17, 2005 Issued
Array ( [id] => 7136816 [patent_doc_number] => 20050181528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Solid state imaging device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/101564 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5764 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20050181528.pdf [firstpage_image] =>[orig_patent_app_number] => 11101564 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/101564
Method of fabricating solid state imaging device including filling interelectrode spacings Apr 7, 2005 Issued
Array ( [id] => 7604948 [patent_doc_number] => 07115982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Semiconductor component having stiffener, stacked dice and circuit decals' [patent_app_type] => utility [patent_app_number] => 11/099374 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 7594 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115982.pdf [firstpage_image] =>[orig_patent_app_number] => 11099374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/099374
Semiconductor component having stiffener, stacked dice and circuit decals Apr 4, 2005 Issued
Array ( [id] => 7002469 [patent_doc_number] => 20050167782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Semiconductor device having an aligned transistor and capacitive element' [patent_app_type] => utility [patent_app_number] => 11/098070 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4098 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167782.pdf [firstpage_image] =>[orig_patent_app_number] => 11098070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/098070
Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element Apr 3, 2005 Issued
Array ( [id] => 5843640 [patent_doc_number] => 20060121725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Method and system for electroprocessing conductive layers' [patent_app_type] => utility [patent_app_number] => 11/088324 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6094 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20060121725.pdf [firstpage_image] =>[orig_patent_app_number] => 11088324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088324
Method and system for electroprocessing conductive layers Mar 22, 2005 Issued
Menu