Search

Peter M. Poon

Supervisory Patent Examiner (ID: 9670, Phone: (571)272-6891 , Office: P/3643 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3103, 3643, 3644
Total Applications
884
Issued Applications
571
Pending Applications
66
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7039580 [patent_doc_number] => 20050158969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Control of thermal donor formation in high resistivity CZ silicon' [patent_app_type] => utility [patent_app_number] => 11/082267 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13134 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158969.pdf [firstpage_image] =>[orig_patent_app_number] => 11082267 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082267
Method for controlling of thermal donor formation in high resistivity CZ silicon Mar 16, 2005 Issued
Array ( [id] => 637798 [patent_doc_number] => 07125751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Semiconductor device and method for the fabrication thereof grinding frame portion such that plural electrode constituent portions' [patent_app_type] => utility [patent_app_number] => 11/042163 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 42 [patent_no_of_words] => 13959 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/125/07125751.pdf [firstpage_image] =>[orig_patent_app_number] => 11042163 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042163
Semiconductor device and method for the fabrication thereof grinding frame portion such that plural electrode constituent portions Jan 25, 2005 Issued
Array ( [id] => 672929 [patent_doc_number] => 07091532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Light shield process for solid-state image sensors' [patent_app_type] => utility [patent_app_number] => 11/042936 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1190 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091532.pdf [firstpage_image] =>[orig_patent_app_number] => 11042936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042936
Light shield process for solid-state image sensors Jan 24, 2005 Issued
Array ( [id] => 535776 [patent_doc_number] => 07180147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Microelectronic structure with a high germanium concentration silicon germanium alloy including a graded buffer layer' [patent_app_type] => utility [patent_app_number] => 11/035628 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4292 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180147.pdf [firstpage_image] =>[orig_patent_app_number] => 11035628 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035628
Microelectronic structure with a high germanium concentration silicon germanium alloy including a graded buffer layer Jan 11, 2005 Issued
Array ( [id] => 535786 [patent_doc_number] => 07180148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Optical system with a high germanium concentration silicon germanium alloy including a graded buffer layer' [patent_app_type] => utility [patent_app_number] => 11/035921 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4291 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180148.pdf [firstpage_image] =>[orig_patent_app_number] => 11035921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035921
Optical system with a high germanium concentration silicon germanium alloy including a graded buffer layer Jan 11, 2005 Issued
Array ( [id] => 7050890 [patent_doc_number] => 20050186777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Methods of fabricating interconnects for semiconductor components' [patent_app_type] => utility [patent_app_number] => 11/028918 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7034 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186777.pdf [firstpage_image] =>[orig_patent_app_number] => 11028918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028918
Methods of fabricating interconnects for semiconductor components including a through hole entirely through the component and forming a metal nitride including separate precursor cycles Jan 2, 2005 Issued
Array ( [id] => 518156 [patent_doc_number] => 07189642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components' [patent_app_type] => utility [patent_app_number] => 11/028892 [patent_app_country] => US [patent_app_date] => 2005-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7068 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/189/07189642.pdf [firstpage_image] =>[orig_patent_app_number] => 11028892 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028892
Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness of angstroms and a low temperature for semiconductor components Jan 2, 2005 Issued
Array ( [id] => 7097981 [patent_doc_number] => 20050130440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (PECVD)' [patent_app_type] => utility [patent_app_number] => 11/021319 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130440.pdf [firstpage_image] =>[orig_patent_app_number] => 11021319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021319
Low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (PECVD) Dec 21, 2004 Issued
Array ( [id] => 7213044 [patent_doc_number] => 20050259708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Photonic integrated device using reverse-mesa structure and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/991614 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20050259708.pdf [firstpage_image] =>[orig_patent_app_number] => 10991614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991614
Photonic integrated device using reverse-mesa structure and method for fabricating the same Nov 17, 2004 Issued
Array ( [id] => 6991070 [patent_doc_number] => 20050090107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Substrate with enhanced properties for planarization' [patent_app_type] => utility [patent_app_number] => 10/979849 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4334 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20050090107.pdf [firstpage_image] =>[orig_patent_app_number] => 10979849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979849
Substrate with enhanced properties for planarization Oct 31, 2004 Issued
Array ( [id] => 485346 [patent_doc_number] => 07217580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Method for processing an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/973704 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 7816 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217580.pdf [firstpage_image] =>[orig_patent_app_number] => 10973704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973704
Method for processing an integrated circuit Oct 25, 2004 Issued
Array ( [id] => 7080514 [patent_doc_number] => 20050045894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor light emitting device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 10/962025 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16118 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045894.pdf [firstpage_image] =>[orig_patent_app_number] => 10962025 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962025
Semiconductor light emitting device and fabrication method thereof Oct 7, 2004 Issued
Array ( [id] => 478631 [patent_doc_number] => 07223706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Method for forming plasma enhanced deposited, fully oxidized PSG film' [patent_app_type] => utility [patent_app_number] => 10/953573 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1128 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/223/07223706.pdf [firstpage_image] =>[orig_patent_app_number] => 10953573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953573
Method for forming plasma enhanced deposited, fully oxidized PSG film Sep 29, 2004 Issued
Array ( [id] => 1018646 [patent_doc_number] => 06891228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture' [patent_app_type] => utility [patent_app_number] => 10/952286 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 5966 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891228.pdf [firstpage_image] =>[orig_patent_app_number] => 10952286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952286
CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture Sep 27, 2004 Issued
Array ( [id] => 679663 [patent_doc_number] => 07084029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor' [patent_app_type] => utility [patent_app_number] => 10/948574 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6524 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084029.pdf [firstpage_image] =>[orig_patent_app_number] => 10948574 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948574
Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor Sep 23, 2004 Issued
Array ( [id] => 500040 [patent_doc_number] => 07205171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Thin film transistor and manufacturing method thereof including a lightly doped channel' [patent_app_type] => utility [patent_app_number] => 10/711509 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4059 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205171.pdf [firstpage_image] =>[orig_patent_app_number] => 10711509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/711509
Thin film transistor and manufacturing method thereof including a lightly doped channel Sep 22, 2004 Issued
Array ( [id] => 988406 [patent_doc_number] => 06921961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region' [patent_app_type] => utility [patent_app_number] => 10/946758 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 4121 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921961.pdf [firstpage_image] =>[orig_patent_app_number] => 10946758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/946758
Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region Sep 21, 2004 Issued
Array ( [id] => 525170 [patent_doc_number] => 07183150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Resist protect oxide structure of sub-micron salicide process' [patent_app_type] => utility [patent_app_number] => 10/946406 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4062 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183150.pdf [firstpage_image] =>[orig_patent_app_number] => 10946406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/946406
Resist protect oxide structure of sub-micron salicide process Sep 20, 2004 Issued
Array ( [id] => 530349 [patent_doc_number] => 07183625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Embedded MIM capacitor and zigzag inductor scheme' [patent_app_type] => utility [patent_app_number] => 10/926836 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 4233 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183625.pdf [firstpage_image] =>[orig_patent_app_number] => 10926836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/926836
Embedded MIM capacitor and zigzag inductor scheme Aug 25, 2004 Issued
Array ( [id] => 790850 [patent_doc_number] => 06984874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT' [patent_app_type] => utility [patent_app_number] => 10/915131 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/984/06984874.pdf [firstpage_image] =>[orig_patent_app_number] => 10915131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915131
Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT Aug 9, 2004 Issued
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