Search

Peter M. Poon

Supervisory Patent Examiner (ID: 9670, Phone: (571)272-6891 , Office: P/3643 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3103, 3643, 3644
Total Applications
884
Issued Applications
571
Pending Applications
66
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6978070 [patent_doc_number] => 20050287788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Manufacturing method of nanowire array' [patent_app_type] => utility [patent_app_number] => 10/914273 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1371 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287788.pdf [firstpage_image] =>[orig_patent_app_number] => 10914273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/914273
Manufacturing method of nanowire array Aug 8, 2004 Abandoned
Array ( [id] => 428614 [patent_doc_number] => 07268048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Methods for elimination of arsenic based defects in semiconductor devices with isolation regions' [patent_app_type] => utility [patent_app_number] => 10/913214 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2792 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268048.pdf [firstpage_image] =>[orig_patent_app_number] => 10913214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/913214
Methods for elimination of arsenic based defects in semiconductor devices with isolation regions Aug 5, 2004 Issued
Array ( [id] => 7429680 [patent_doc_number] => 20040266134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Novel approach to improve line end shortening' [patent_app_type] => new [patent_app_number] => 10/899927 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5272 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266134.pdf [firstpage_image] =>[orig_patent_app_number] => 10899927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899927
Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers Jul 26, 2004 Issued
Array ( [id] => 7605479 [patent_doc_number] => 07115450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask' [patent_app_type] => utility [patent_app_number] => 10/899567 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 5339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115450.pdf [firstpage_image] =>[orig_patent_app_number] => 10899567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899567
Approach to improve line end shortening including simultaneous trimming of photosensitive layer and hardmask Jul 26, 2004 Issued
Array ( [id] => 6971565 [patent_doc_number] => 20050037275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Pattern forming method and wiring pattern forming method, and electro-optic device and electronic equipment' [patent_app_type] => utility [patent_app_number] => 10/898344 [patent_app_country] => US [patent_app_date] => 2004-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15416 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20050037275.pdf [firstpage_image] =>[orig_patent_app_number] => 10898344 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898344
Pattern forming method and wiring pattern forming method, and electro-optic device and electronic equipment Jul 25, 2004 Issued
Array ( [id] => 493346 [patent_doc_number] => 07211454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Manufacturing method of a light emitting device including moving the source of the vapor deposition parallel to the substrate' [patent_app_type] => utility [patent_app_number] => 10/894434 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 35 [patent_no_of_words] => 13957 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/211/07211454.pdf [firstpage_image] =>[orig_patent_app_number] => 10894434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894434
Manufacturing method of a light emitting device including moving the source of the vapor deposition parallel to the substrate Jul 19, 2004 Issued
Array ( [id] => 935422 [patent_doc_number] => 06974771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Methods and apparatus for forming barrier layers in high aspect ratio vias' [patent_app_type] => utility [patent_app_number] => 10/894774 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 14859 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/974/06974771.pdf [firstpage_image] =>[orig_patent_app_number] => 10894774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894774
Methods and apparatus for forming barrier layers in high aspect ratio vias Jul 19, 2004 Issued
Array ( [id] => 690427 [patent_doc_number] => 07074663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Method of making semiconductor device including a first set of windows in a mask with larger ratio of surface area than a second set of windows' [patent_app_type] => utility [patent_app_number] => 10/890688 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9665 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 568 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/074/07074663.pdf [firstpage_image] =>[orig_patent_app_number] => 10890688 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/890688
Method of making semiconductor device including a first set of windows in a mask with larger ratio of surface area than a second set of windows Jul 13, 2004 Issued
Array ( [id] => 7605024 [patent_doc_number] => 07115905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Semiconductor device including forming an amorphous silicon layer over and reacting with a silicide layer' [patent_app_type] => utility [patent_app_number] => 10/889134 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7760 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115905.pdf [firstpage_image] =>[orig_patent_app_number] => 10889134 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889134
Semiconductor device including forming an amorphous silicon layer over and reacting with a silicide layer Jul 12, 2004 Issued
Array ( [id] => 7089201 [patent_doc_number] => 20050009314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method for forming a bonding pad of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/889398 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009314.pdf [firstpage_image] =>[orig_patent_app_number] => 10889398 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889398
Method for forming a bonding pad of a semiconductor device including a plasma treatment Jul 11, 2004 Issued
Array ( [id] => 931114 [patent_doc_number] => 06979618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method of manufacturing NAND flash device' [patent_app_type] => utility [patent_app_number] => 10/887964 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2139 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979618.pdf [firstpage_image] =>[orig_patent_app_number] => 10887964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887964
Method of manufacturing NAND flash device Jul 8, 2004 Issued
Array ( [id] => 7196668 [patent_doc_number] => 20050051436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method of submicron metallization using electrochemical deposition of recesses including a first deposition at a first current density and a second deposition at an increased current density' [patent_app_type] => utility [patent_app_number] => 10/882664 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3204 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051436.pdf [firstpage_image] =>[orig_patent_app_number] => 10882664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882664
Method of submicron metallization using electrochemical deposition of recesses including a first deposition at a first current density and a second deposition at an increased current density Jun 30, 2004 Issued
Array ( [id] => 7264067 [patent_doc_number] => 20040241944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Nonvolatile memory device' [patent_app_type] => new [patent_app_number] => 10/878247 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 15101 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241944.pdf [firstpage_image] =>[orig_patent_app_number] => 10878247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878247
Method for forming nonvolatile memory device including insulating film containing nitrogen (nitride) Jun 28, 2004 Issued
Array ( [id] => 7058881 [patent_doc_number] => 20050001240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor wafer having different impurity concentrations in respective regions' [patent_app_type] => utility [patent_app_number] => 10/875383 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001240.pdf [firstpage_image] =>[orig_patent_app_number] => 10875383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875383
Semiconductor wafer having different impurity concentrations in respective regions Jun 24, 2004 Issued
Array ( [id] => 6929040 [patent_doc_number] => 20050280073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'System and method of forming a split-gate flash memory structure' [patent_app_type] => utility [patent_app_number] => 10/873694 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2958 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20050280073.pdf [firstpage_image] =>[orig_patent_app_number] => 10873694 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873694
System and method of forming a split-gate flash memory structure Jun 21, 2004 Issued
Array ( [id] => 7056089 [patent_doc_number] => 20050277264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'IMPROVED PROCESS FOR FORMING A BURIED PLATE' [patent_app_type] => utility [patent_app_number] => 10/710045 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20050277264.pdf [firstpage_image] =>[orig_patent_app_number] => 10710045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710045
Process for forming a buried plate Jun 14, 2004 Issued
Array ( [id] => 7317836 [patent_doc_number] => 20040224450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Method of forming insulating film and method of fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/863285 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16394 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20040224450.pdf [firstpage_image] =>[orig_patent_app_number] => 10863285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863285
Method of forming insulating film and method of fabricating semiconductor device including plasma bias for forming a second insulating film Jun 8, 2004 Issued
Array ( [id] => 1005356 [patent_doc_number] => 06905951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Method of forming a device substrate and semiconductor package including a pyramid contact' [patent_app_type] => utility [patent_app_number] => 10/862403 [patent_app_country] => US [patent_app_date] => 2004-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 6077 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905951.pdf [firstpage_image] =>[orig_patent_app_number] => 10862403 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/862403
Method of forming a device substrate and semiconductor package including a pyramid contact Jun 7, 2004 Issued
Array ( [id] => 749587 [patent_doc_number] => 07022560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method to manufacture high voltage MOS transistor by ion implantation' [patent_app_type] => utility [patent_app_number] => 10/853508 [patent_app_country] => US [patent_app_date] => 2004-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022560.pdf [firstpage_image] =>[orig_patent_app_number] => 10853508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853508
Method to manufacture high voltage MOS transistor by ion implantation May 24, 2004 Issued
Array ( [id] => 7375843 [patent_doc_number] => 20040219762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same' [patent_app_type] => new [patent_app_number] => 10/851202 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 23333 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20040219762.pdf [firstpage_image] =>[orig_patent_app_number] => 10851202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/851202
Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same May 23, 2004 Issued
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