| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 393927
[patent_doc_number] => 07297620
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Method of forming an oxide layer including increasing the temperature during oxidation'
[patent_app_type] => utility
[patent_app_number] => 10/839934
[patent_app_country] => US
[patent_app_date] => 2004-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 12749
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/297/07297620.pdf
[firstpage_image] =>[orig_patent_app_number] => 10839934
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/839934 | Method of forming an oxide layer including increasing the temperature during oxidation | May 5, 2004 | Issued |
Array
(
[id] => 7174396
[patent_doc_number] => 20040201104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation'
[patent_app_type] => new
[patent_app_number] => 10/837596
[patent_app_country] => US
[patent_app_date] => 2004-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10051
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20040201104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10837596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/837596 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | May 3, 2004 | Issued |
Array
(
[id] => 7375907
[patent_doc_number] => 20040219773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-04
[patent_title] => 'Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method'
[patent_app_type] => new
[patent_app_number] => 10/835044
[patent_app_country] => US
[patent_app_date] => 2004-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4830
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0219/20040219773.pdf
[firstpage_image] =>[orig_patent_app_number] => 10835044
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/835044 | Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method | Apr 29, 2004 | Issued |
Array
(
[id] => 710723
[patent_doc_number] => 07056799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Method of forming wing gate transistor for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/820664
[patent_app_country] => US
[patent_app_date] => 2004-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 2563
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/056/07056799.pdf
[firstpage_image] =>[orig_patent_app_number] => 10820664
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/820664 | Method of forming wing gate transistor for integrated circuits | Apr 6, 2004 | Issued |
Array
(
[id] => 7338592
[patent_doc_number] => 20040245616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Stacked device underfill and a method of fabrication'
[patent_app_type] => new
[patent_app_number] => 10/814083
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5573
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20040245616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10814083
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/814083 | Stacked device underfill and a method of fabrication | Mar 29, 2004 | Issued |
Array
(
[id] => 6955763
[patent_doc_number] => 20050212133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-29
[patent_title] => 'UNDER BUMP METALLIZATION LAYER TO ENABLE USE OF HIGH TIN CONTENT SOLDER BUMPS'
[patent_app_type] => utility
[patent_app_number] => 10/812464
[patent_app_country] => US
[patent_app_date] => 2004-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2711
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20050212133.pdf
[firstpage_image] =>[orig_patent_app_number] => 10812464
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/812464 | Under bump metallization layer to enable use of high tin content solder bumps | Mar 28, 2004 | Issued |
Array
(
[id] => 7334103
[patent_doc_number] => 20040188755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/802824
[patent_app_country] => US
[patent_app_date] => 2004-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6588
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20040188755.pdf
[firstpage_image] =>[orig_patent_app_number] => 10802824
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/802824 | Method of manufacture of a silicon carbide MOSFET including a masking with a tapered shape and implanting ions at an angle | Mar 17, 2004 | Issued |
Array
(
[id] => 5113102
[patent_doc_number] => 20070197017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-23
[patent_title] => 'Manufacturing method of semiconductor module'
[patent_app_type] => utility
[patent_app_number] => 10/591723
[patent_app_country] => US
[patent_app_date] => 2004-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 14440
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20070197017.pdf
[firstpage_image] =>[orig_patent_app_number] => 10591723
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/591723 | Manufacturing method of semiconductor module including solid-liquid diffusion joining steps | Mar 1, 2004 | Issued |
Array
(
[id] => 641711
[patent_doc_number] => 07122410
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-17
[patent_title] => 'Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate'
[patent_app_type] => utility
[patent_app_number] => 10/790974
[patent_app_country] => US
[patent_app_date] => 2004-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 6529
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/122/07122410.pdf
[firstpage_image] =>[orig_patent_app_number] => 10790974
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/790974 | Polysilicon line having a metal silicide region enabling linewidth scaling including forming a second metal silicide region on the substrate | Mar 1, 2004 | Issued |
Array
(
[id] => 1009342
[patent_doc_number] => 06900104
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-31
[patent_title] => 'Method of forming offset spacer manufacturing for critical dimension precision'
[patent_app_type] => utility
[patent_app_number] => 10/788754
[patent_app_country] => US
[patent_app_date] => 2004-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2271
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/900/06900104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10788754
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/788754 | Method of forming offset spacer manufacturing for critical dimension precision | Feb 26, 2004 | Issued |
Array
(
[id] => 7406318
[patent_doc_number] => 20040175853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/785944
[patent_app_country] => US
[patent_app_date] => 2004-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5609
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20040175853.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785944
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785944 | Method for fabricating a semiconductor device including exposing a group III-V semiconductor to an ammonia plasma | Feb 25, 2004 | Issued |
Array
(
[id] => 698760
[patent_doc_number] => 07067338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Method of manufacturing a display device including forming electric connections on a substrate, conductor patterns on a second substrate and coupling the connections'
[patent_app_type] => utility
[patent_app_number] => 10/787674
[patent_app_country] => US
[patent_app_date] => 2004-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2798
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10787674
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/787674 | Method of manufacturing a display device including forming electric connections on a substrate, conductor patterns on a second substrate and coupling the connections | Feb 25, 2004 | Issued |
Array
(
[id] => 634069
[patent_doc_number] => 07129125
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Semiconductor device and manufacturing method thereof including heating a silicon oxide in a helium gas'
[patent_app_type] => utility
[patent_app_number] => 10/785074
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 24
[patent_no_of_words] => 5133
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129125.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785074 | Semiconductor device and manufacturing method thereof including heating a silicon oxide in a helium gas | Feb 24, 2004 | Issued |
Array
(
[id] => 982318
[patent_doc_number] => 06927162
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-08-09
[patent_title] => 'Method of forming a contact in a semiconductor device with formation of silicide prior to plasma treatment'
[patent_app_type] => utility
[patent_app_number] => 10/782874
[patent_app_country] => US
[patent_app_date] => 2004-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2787
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/927/06927162.pdf
[firstpage_image] =>[orig_patent_app_number] => 10782874
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/782874 | Method of forming a contact in a semiconductor device with formation of silicide prior to plasma treatment | Feb 22, 2004 | Issued |
Array
(
[id] => 686612
[patent_doc_number] => 07078302
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-18
[patent_title] => 'Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal'
[patent_app_type] => utility
[patent_app_number] => 10/784904
[patent_app_country] => US
[patent_app_date] => 2004-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3653
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/078/07078302.pdf
[firstpage_image] =>[orig_patent_app_number] => 10784904
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/784904 | Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal | Feb 22, 2004 | Issued |
Array
(
[id] => 7050903
[patent_doc_number] => 20050186790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'METHODS OF FABRICATING INTERCONNECTS FOR SEMICONDUCTOR COMPONENTS'
[patent_app_type] => utility
[patent_app_number] => 10/784074
[patent_app_country] => US
[patent_app_date] => 2004-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7036
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20050186790.pdf
[firstpage_image] =>[orig_patent_app_number] => 10784074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/784074 | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling | Feb 19, 2004 | Issued |
Array
(
[id] => 641703
[patent_doc_number] => 07122402
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-17
[patent_title] => 'Method of manufacturing a semiconductor device using a rigid substrate including the vent-end edge portion of the substrate has a thickness smaller than the other portions of the substrate'
[patent_app_type] => utility
[patent_app_number] => 10/781794
[patent_app_country] => US
[patent_app_date] => 2004-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 7312
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/122/07122402.pdf
[firstpage_image] =>[orig_patent_app_number] => 10781794
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/781794 | Method of manufacturing a semiconductor device using a rigid substrate including the vent-end edge portion of the substrate has a thickness smaller than the other portions of the substrate | Feb 19, 2004 | Issued |
Array
(
[id] => 7609871
[patent_doc_number] => 06998316
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Method for fabricating read only memory including a first and second exposures to a photoresist layer'
[patent_app_type] => utility
[patent_app_number] => 10/708228
[patent_app_country] => US
[patent_app_date] => 2004-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 36
[patent_no_of_words] => 9682
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/998/06998316.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708228 | Method for fabricating read only memory including a first and second exposures to a photoresist layer | Feb 17, 2004 | Issued |
Array
(
[id] => 668378
[patent_doc_number] => 07094618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape'
[patent_app_type] => utility
[patent_app_number] => 10/778277
[patent_app_country] => US
[patent_app_date] => 2004-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6155
[patent_no_of_claims] => 72
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/094/07094618.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778277
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778277 | Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape | Feb 12, 2004 | Issued |
Array
(
[id] => 1012647
[patent_doc_number] => 06897118
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-24
[patent_title] => 'Method of multiple pulse laser annealing to activate ultra-shallow junctions'
[patent_app_type] => utility
[patent_app_number] => 10/776794
[patent_app_country] => US
[patent_app_date] => 2004-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4389
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/897/06897118.pdf
[firstpage_image] =>[orig_patent_app_number] => 10776794
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/776794 | Method of multiple pulse laser annealing to activate ultra-shallow junctions | Feb 10, 2004 | Issued |