Search

Peter M. Poon

Supervisory Patent Examiner (ID: 9670, Phone: (571)272-6891 , Office: P/3643 )

Most Active Art Unit
3103
Art Unit(s)
3613, 3103, 3643, 3644
Total Applications
884
Issued Applications
571
Pending Applications
66
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7335581 [patent_doc_number] => 20040132283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Methods of forming metal wiring of semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/741834 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1970 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20040132283.pdf [firstpage_image] =>[orig_patent_app_number] => 10741834 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/741834
Methods of forming metal wiring of semiconductor devices including sintering the wiring layers and forming a via hole with a barrier metal Dec 18, 2003 Issued
Array ( [id] => 953866 [patent_doc_number] => 06958280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Method for manufacturing alignment mark of semiconductor device using STI process' [patent_app_type] => utility [patent_app_number] => 10/737784 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1418 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958280.pdf [firstpage_image] =>[orig_patent_app_number] => 10737784 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737784
Method for manufacturing alignment mark of semiconductor device using STI process Dec 17, 2003 Issued
Array ( [id] => 760847 [patent_doc_number] => 07011999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Method of manufacturing an integrated circuit device including forming an oxidation resistant film over an isolation region and subsequently forming a gate insulating film of a misfet' [patent_app_type] => utility [patent_app_number] => 10/736794 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 14537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/011/07011999.pdf [firstpage_image] =>[orig_patent_app_number] => 10736794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/736794
Method of manufacturing an integrated circuit device including forming an oxidation resistant film over an isolation region and subsequently forming a gate insulating film of a misfet Dec 16, 2003 Issued
Array ( [id] => 701403 [patent_doc_number] => 07063987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Backside failure analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/738144 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2250 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/063/07063987.pdf [firstpage_image] =>[orig_patent_app_number] => 10738144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738144
Backside failure analysis of integrated circuits Dec 16, 2003 Issued
Array ( [id] => 746462 [patent_doc_number] => 07026666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Self-aligned NPN transistor with raised extrinsic base' [patent_app_type] => utility [patent_app_number] => 10/734928 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3007 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026666.pdf [firstpage_image] =>[orig_patent_app_number] => 10734928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734928
Self-aligned NPN transistor with raised extrinsic base Dec 11, 2003 Issued
Array ( [id] => 7295891 [patent_doc_number] => 20040124461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Trench-gate semiconductor devices, and their manufacture' [patent_app_type] => new [patent_app_number] => 10/733214 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6703 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124461.pdf [firstpage_image] =>[orig_patent_app_number] => 10733214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733214
Trench-gate semiconductor devices, and their manufacture Dec 10, 2003 Issued
Array ( [id] => 7423458 [patent_doc_number] => 20040229417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Method of forming film' [patent_app_type] => new [patent_app_number] => 10/732213 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4334 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20040229417.pdf [firstpage_image] =>[orig_patent_app_number] => 10732213 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732213
Method of forming film including a comb tooth patterning film Dec 10, 2003 Issued
Array ( [id] => 679648 [patent_doc_number] => 07084022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Method of manufacturing a semiconductor device including forming a pattern, an interlayer insulation film, exposing the patterning and flattening' [patent_app_type] => utility [patent_app_number] => 10/730903 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 56 [patent_no_of_words] => 6944 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084022.pdf [firstpage_image] =>[orig_patent_app_number] => 10730903 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730903
Method of manufacturing a semiconductor device including forming a pattern, an interlayer insulation film, exposing the patterning and flattening Dec 9, 2003 Issued
Array ( [id] => 7154226 [patent_doc_number] => 20050082532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Light emitting device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/731033 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082532.pdf [firstpage_image] =>[orig_patent_app_number] => 10731033 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731033
Light emitting structure including an exposed electrode overlapping a wiring or conductive layer Dec 9, 2003 Issued
Array ( [id] => 7471347 [patent_doc_number] => 20040121521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods of fabrication and assemblies' [patent_app_type] => new [patent_app_number] => 10/732558 [patent_app_country] => US [patent_app_date] => 2003-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7170 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121521.pdf [firstpage_image] =>[orig_patent_app_number] => 10732558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/732558
Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof Dec 9, 2003 Issued
Array ( [id] => 701470 [patent_doc_number] => 07064022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method of forming merged FET inverter/logic gate' [patent_app_type] => utility [patent_app_number] => 10/728844 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 4098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064022.pdf [firstpage_image] =>[orig_patent_app_number] => 10728844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/728844
Method of forming merged FET inverter/logic gate Dec 7, 2003 Issued
Array ( [id] => 978967 [patent_doc_number] => 06929996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Corner rounding process for partial vertical transistor' [patent_app_type] => utility [patent_app_number] => 10/726434 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 1857 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/929/06929996.pdf [firstpage_image] =>[orig_patent_app_number] => 10726434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726434
Corner rounding process for partial vertical transistor Dec 2, 2003 Issued
Array ( [id] => 658081 [patent_doc_number] => 07105384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Circuit device manufacturing method including mounting circuit elements on a conductive foil, forming separation grooves in the foil, and etching the rear of the foil' [patent_app_type] => utility [patent_app_number] => 10/724954 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 4162 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105384.pdf [firstpage_image] =>[orig_patent_app_number] => 10724954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724954
Circuit device manufacturing method including mounting circuit elements on a conductive foil, forming separation grooves in the foil, and etching the rear of the foil Nov 30, 2003 Issued
Array ( [id] => 6939289 [patent_doc_number] => 20050112852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Using acoustic energy to activate implanted species' [patent_app_type] => utility [patent_app_number] => 10/720934 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1347 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112852.pdf [firstpage_image] =>[orig_patent_app_number] => 10720934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/720934
Using acoustic energy including two lasers to activate implanted species Nov 23, 2003 Issued
Array ( [id] => 7429320 [patent_doc_number] => 20040161908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Method for fabricating a semiconductor device having a heat radiation layer' [patent_app_type] => new [patent_app_number] => 10/717934 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7135 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20040161908.pdf [firstpage_image] =>[orig_patent_app_number] => 10717934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717934
Method for fabricating a semiconductor device having a heat radiation layer including forming scribe lines and dicing Nov 20, 2003 Issued
Array ( [id] => 7408942 [patent_doc_number] => 20040106271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Processing method of forming MRAM circuitry' [patent_app_type] => new [patent_app_number] => 10/719634 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3417 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106271.pdf [firstpage_image] =>[orig_patent_app_number] => 10719634 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/719634
Processing method of forming MRAM circuitry Nov 20, 2003 Issued
Array ( [id] => 7471945 [patent_doc_number] => 20040097024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Interconnections including multi-layer metal film stack for improving corrosion and heat resistances' [patent_app_type] => new [patent_app_number] => 10/705864 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20040097024.pdf [firstpage_image] =>[orig_patent_app_number] => 10705864 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705864
Method for forming interconnections including multi-layer metal film stack for improving corrosion and heat resistances Nov 12, 2003 Issued
Array ( [id] => 7466943 [patent_doc_number] => 20040102035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Semiconductor devices and methods for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/705480 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4138 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102035.pdf [firstpage_image] =>[orig_patent_app_number] => 10705480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705480
Method of fabricating semiconductor device including forming contact hole with anisotropic and isotropic etching and forming discontinuous barrier layer Nov 9, 2003 Issued
Array ( [id] => 7466923 [patent_doc_number] => 20040102032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Selectively converted inter-layer dielectric' [patent_app_type] => new [patent_app_number] => 10/701251 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4795 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102032.pdf [firstpage_image] =>[orig_patent_app_number] => 10701251 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701251
Method of forming a selectively converted inter-layer dielectric using a porogen material Nov 2, 2003 Issued
Array ( [id] => 694621 [patent_doc_number] => 07071014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Methods for preserving strained semiconductor substrate layers during CMOS processing' [patent_app_type] => utility [patent_app_number] => 10/696994 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6267 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/071/07071014.pdf [firstpage_image] =>[orig_patent_app_number] => 10696994 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696994
Methods for preserving strained semiconductor substrate layers during CMOS processing Oct 29, 2003 Issued
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