Search

Peter M Poon

Supervisory Patent Examiner (ID: 5136, Phone: (571)272-6891 , Office: P/3643 )

Most Active Art Unit
3103
Art Unit(s)
3103, 3613, 3644, 3643
Total Applications
864
Issued Applications
565
Pending Applications
59
Abandoned Applications
240

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18421661 [patent_doc_number] => 20230176125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => VIRTUAL MACHINE TESTING OF ELECTRICAL MACHINES USING PHYSICAL DOMAIN PERFORMANCE SIGNATURES [patent_app_type] => utility [patent_app_number] => 17/921136 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17921136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/921136
VIRTUAL MACHINE TESTING OF ELECTRICAL MACHINES USING PHYSICAL DOMAIN PERFORMANCE SIGNATURES Apr 27, 2021 Pending
Array ( [id] => 17296036 [patent_doc_number] => 20210391875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Decoding circuit and decoding method based on Viterbi algorithm [patent_app_type] => utility [patent_app_number] => 17/239734 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239734 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239734
Decoding circuit and decoding method based on Viterbi algorithm Apr 25, 2021 Issued
Array ( [id] => 17189751 [patent_doc_number] => 20210336636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => VARIABLE RATE LOW DENSITY PARITY CHECK DECODER [patent_app_type] => utility [patent_app_number] => 17/239370 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239370
Variable rate low density parity check decoder Apr 22, 2021 Issued
Array ( [id] => 18345941 [patent_doc_number] => 20230134051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => MULTI-STAGE BURST DETECTION FOR COMMUNICATIONS SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/917532 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17917532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/917532
MULTI-STAGE BURST DETECTION FOR COMMUNICATIONS SYSTEMS Apr 5, 2021 Pending
Array ( [id] => 17918748 [patent_doc_number] => 20220321144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => METHODS AND SYSTEMS OF STALL MITIGATION IN ITERATIVE DECODERS [patent_app_type] => utility [patent_app_number] => 17/223804 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223804
Methods and systems of stall mitigation in iterative decoders Apr 5, 2021 Issued
Array ( [id] => 18780233 [patent_doc_number] => 11821945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Full pad coverage boundary scan [patent_app_type] => utility [patent_app_number] => 17/217391 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5089 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217391 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217391
Full pad coverage boundary scan Mar 29, 2021 Issued
Array ( [id] => 16965354 [patent_doc_number] => 20210216853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => YIELD IMPROVEMENTS FOR THREE-DIMENSIONALLY STACKED NEURAL NETWORK ACCELERATORS [patent_app_type] => utility [patent_app_number] => 17/213871 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213871
Yield improvements for three-dimensionally stacked neural network accelerators Mar 25, 2021 Issued
Array ( [id] => 19329397 [patent_doc_number] => 12047092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Checksum addition method, checksum addition device, and sensor system [patent_app_type] => utility [patent_app_number] => 17/906511 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3566 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906511
Checksum addition method, checksum addition device, and sensor system Mar 25, 2021 Issued
Array ( [id] => 17510083 [patent_doc_number] => 20220103187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => LOW-DENSITY PARITY-CHECK (LDPC) DECODER OF RECONSTRUCTION-COMPUTATION-QUANTIZATION (RCQ) APPROACH FOR A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/204936 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204936
Low-density parity-check (LDCP) decoder of reconstruction-computation-quantization (RCQ) approach for a storage device Mar 16, 2021 Issued
Array ( [id] => 19184312 [patent_doc_number] => 11990921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => List decoding of polarization-adjusted convolutional codes [patent_app_type] => utility [patent_app_number] => 17/906447 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906447
List decoding of polarization-adjusted convolutional codes Mar 15, 2021 Issued
Array ( [id] => 17731442 [patent_doc_number] => 11387846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same [patent_app_type] => utility [patent_app_number] => 17/202035 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5638 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202035
Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same Mar 14, 2021 Issued
Array ( [id] => 17819135 [patent_doc_number] => 11424763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same [patent_app_type] => utility [patent_app_number] => 17/202050 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7077 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 1040 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202050
Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same Mar 14, 2021 Issued
Array ( [id] => 17788442 [patent_doc_number] => 11411583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Deinterleaving method and deinterleaving system performing the same [patent_app_type] => utility [patent_app_number] => 17/199605 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5471 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199605
Deinterleaving method and deinterleaving system performing the same Mar 11, 2021 Issued
Array ( [id] => 17824521 [patent_doc_number] => 11429469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Defective bit line management in connection with a memory access [patent_app_type] => utility [patent_app_number] => 17/195579 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195579
Defective bit line management in connection with a memory access Mar 7, 2021 Issued
Array ( [id] => 17853901 [patent_doc_number] => 20220283943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => HIGH-THROUGHPUT SOFTWARE-DEFINED CONVOLUTIONAL INTERLEAVERS AND DE-INTERLEAVERS [patent_app_type] => utility [patent_app_number] => 17/193354 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193354
High-throughput software-defined convolutional interleavers and de-interleavers Mar 4, 2021 Issued
Array ( [id] => 16903044 [patent_doc_number] => 20210181960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SOLID STATE STORAGE DEVICE WITH QUICK BOOT FROM NAND MEDIA [patent_app_type] => utility [patent_app_number] => 17/189502 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189502
Solid state storage device with quick boot from NAND media Mar 1, 2021 Issued
Array ( [id] => 18271870 [patent_doc_number] => 20230093112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => COMMUNICATION DEVICE AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 17/798888 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798888 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/798888
COMMUNICATION DEVICE AND COMMUNICATION METHOD Feb 15, 2021 Pending
Array ( [id] => 16848231 [patent_doc_number] => 20210148976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Self Test for Safety Logic [patent_app_type] => utility [patent_app_number] => 17/160461 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160461
Self test for safety logic Jan 27, 2021 Issued
Array ( [id] => 17803904 [patent_doc_number] => 11418221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Method and polar code decoder for determining to-be-flipped bit position [patent_app_type] => utility [patent_app_number] => 17/156647 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3443 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156647
Method and polar code decoder for determining to-be-flipped bit position Jan 24, 2021 Issued
Array ( [id] => 17589567 [patent_doc_number] => 11327840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-10 [patent_title] => Multi-stage data recovery in a distributed storage network [patent_app_type] => utility [patent_app_number] => 17/248424 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248424
Multi-stage data recovery in a distributed storage network Jan 24, 2021 Issued
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