Peter R. Brown

Array ( [id] => 11539393 [patent_doc_number] => 09613808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-04 [patent_title] => 'Method of forming multilayer hard mask with treatment for removing impurities and forming dangling bonds' [patent_app_type] => utility [patent_app_number] => 15/001094 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2289 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10780329 [patent_doc_number] => 20160126484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'Optoelectronic Devices Made Using Layers Detached From Inherently Lamellar Semiconductor Donors' [patent_app_type] => utility [patent_app_number] => 14/995439 [patent_app_country] => US [patent_app_date] => 2016-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10274 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13419911 [patent_doc_number] => 20180261498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => A METHOD TO ACHIEVE A UNIFORM GROUP IV MATERIAL LAYER IN AN ASPECT RATIO TRAPPING TRENCH [patent_app_type] => utility [patent_app_number] => 15/779442 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15779442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15547917 [patent_doc_number] => 10573750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Methods of forming doped source/drain contacts and structures formed thereby [patent_app_type] => utility [patent_app_number] => 15/779485 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6096 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15779485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11300813 [patent_doc_number] => 09508825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method and structure for forming gate contact above active area with trench silicide' [patent_app_type] => utility [patent_app_number] => 14/968267 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5064 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13640579 [patent_doc_number] => 09847250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Flexible display and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/961528 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10826357 [patent_doc_number] => 20160172525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'High-Speed Germanium On Silicon Avalanche Photodiode' [patent_app_type] => utility [patent_app_number] => 14/961675 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11600020 [patent_doc_number] => 09647200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-09 [patent_title] => 'Encapsulation of magnetic tunnel junction structures in organic photopatternable dielectric material' [patent_app_type] => utility [patent_app_number] => 14/961243 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4853 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11673927 [patent_doc_number] => 20170162651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A GATE ALL AROUND STRUCTURE AND A METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/961213 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8683 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12554247 [patent_doc_number] => 10014307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device manufacturing method including implementing elements of memory unit and logic unit [patent_app_type] => utility [patent_app_number] => 14/961525 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11831737 [patent_doc_number] => 09728486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Semiconductor device including a fin pattern' [patent_app_type] => utility [patent_app_number] => 14/961259 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 13192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11891115 [patent_doc_number] => 09761682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Semiconductor device with silicon nitride film on nitride semiconductor layer and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/961545 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9381 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11510399 [patent_doc_number] => 09601569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Semiconductor device having a gate all around structure' [patent_app_type] => utility [patent_app_number] => 14/961378 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 11269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10740950 [patent_doc_number] => 20160087102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A STRAIN FEATURE IN A GATE SPACER AND METHODS OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/959510 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4951 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13514483 [patent_doc_number] => 20180308784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => STACKED DIE PACKAGE WITH THROUGH-MOLD THERMALLY CONDUCTIVE STRUCTURES BETWEEN A BOTTOM DIE AND A THERMALLY CONDUCTIVE MATERIAL [patent_app_type] => utility [patent_app_number] => 15/769705 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11911064 [patent_doc_number] => 09779882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Method of producing supercapacitor electrodes and cells having high active mass loading' [patent_app_type] => utility [patent_app_number] => 14/757124 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 22850 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11802815 [patent_doc_number] => 09543736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-10 [patent_title] => 'Optimized solder pads for solder induced alignment of opto-electronic chips' [patent_app_type] => utility [patent_app_number] => 14/947621 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 6839 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10610906 [patent_doc_number] => 09330946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-03 [patent_title] => 'Method and structure of die stacking using pre-applied underfill' [patent_app_type] => utility [patent_app_number] => 14/946904 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4368 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802807 [patent_doc_number] => 20160148964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'METHOD OF PRODUCING EPITAXIAL SILICON WAFER, EPITAXIAL SILICON WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/946661 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9711 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14151981 [patent_doc_number] => 10256380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Method of producing an optoelectronic component, and optoelectronic component [patent_app_type] => utility [patent_app_number] => 15/524413 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15524413 [rel_patent_id] =>[rel_patent_doc_number] =>)