Peter S. Vasat

Array ( [id] => 5218548 [patent_doc_number] => 20070159859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'VOLTAGE TRANSLATOR CIRCUITS USING CAPACITIVE TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 11/275538 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159859.pdf [firstpage_image] =>[orig_patent_app_number] => 11275538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 412166 [patent_doc_number] => 07282971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Digital delay lock loop' [patent_app_type] => utility [patent_app_number] => 11/319756 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3526 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282971.pdf [firstpage_image] =>[orig_patent_app_number] => 11319756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5909837 [patent_doc_number] => 20060125536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Phase locked loop circuit having deadlock protection circuit and methods of operating same' [patent_app_type] => utility [patent_app_number] => 11/291415 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125536.pdf [firstpage_image] =>[orig_patent_app_number] => 11291415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5878699 [patent_doc_number] => 20060028253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Power-on reset circuit' [patent_app_type] => utility [patent_app_number] => 11/245246 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5063 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20060028253.pdf [firstpage_image] =>[orig_patent_app_number] => 11245246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5838920 [patent_doc_number] => 20060119401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Comparator switching apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/239083 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20060119401.pdf [firstpage_image] =>[orig_patent_app_number] => 11239083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5606147 [patent_doc_number] => 20060267663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Circuit for detecting transitions on either of two signal lines referenced at different power supply levels' [patent_app_type] => utility [patent_app_number] => 11/239194 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1027 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267663.pdf [firstpage_image] =>[orig_patent_app_number] => 11239194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5635387 [patent_doc_number] => 20060066360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Switched operation amplifier' [patent_app_type] => utility [patent_app_number] => 11/236673 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3958 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20060066360.pdf [firstpage_image] =>[orig_patent_app_number] => 11236673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 422311 [patent_doc_number] => 07274245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Voltage transfer circuit' [patent_app_type] => utility [patent_app_number] => 11/162667 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4439 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/274/07274245.pdf [firstpage_image] =>[orig_patent_app_number] => 11162667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5746106 [patent_doc_number] => 20060109036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'POWER-LOW RESET CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/161257 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4360 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109036.pdf [firstpage_image] =>[orig_patent_app_number] => 11161257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5746107 [patent_doc_number] => 20060109037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'POWER-ON RESET CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/161260 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4611 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109037.pdf [firstpage_image] =>[orig_patent_app_number] => 11161260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5713626 [patent_doc_number] => 20060076989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Enhanced phase and frequency detector that improves performance in the presence of a failing clock' [patent_app_type] => utility [patent_app_number] => 11/180279 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3282 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20060076989.pdf [firstpage_image] =>[orig_patent_app_number] => 11180279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 398260 [patent_doc_number] => 07295051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'System and method for monitoring a power supply level' [patent_app_type] => utility [patent_app_number] => 11/153773 [patent_app_country] => US [patent_app_date] => 2005-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6944 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295051.pdf [firstpage_image] =>[orig_patent_app_number] => 11153773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 613340 [patent_doc_number] => 07148740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Boost circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/099260 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4572 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148740.pdf [firstpage_image] =>[orig_patent_app_number] => 11099260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5909854 [patent_doc_number] => 20060125552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Voltage-multiplier circuit' [patent_app_type] => utility [patent_app_number] => 11/098055 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2354 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125552.pdf [firstpage_image] =>[orig_patent_app_number] => 11098055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 488083 [patent_doc_number] => 07218154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-15 [patent_title] => 'Track and hold circuit with operating point sensitive current mode based offset compensation' [patent_app_type] => utility [patent_app_number] => 11/094945 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4623 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218154.pdf [firstpage_image] =>[orig_patent_app_number] => 11094945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7043776 [patent_doc_number] => 20050248371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Current to voltage amplifier' [patent_app_type] => utility [patent_app_number] => 11/083260 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2745 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248371.pdf [firstpage_image] =>[orig_patent_app_number] => 11083260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 454278 [patent_doc_number] => 07248082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Sample-hold circuit' [patent_app_type] => utility [patent_app_number] => 11/076924 [patent_app_country] => US [patent_app_date] => 2005-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4872 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248082.pdf [firstpage_image] =>[orig_patent_app_number] => 11076924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5763559 [patent_doc_number] => 20060017483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Pulse-based high-speed low-power gated flip-flop circuit' [patent_app_type] => utility [patent_app_number] => 11/064892 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5776 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20060017483.pdf [firstpage_image] =>[orig_patent_app_number] => 11064892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7208183 [patent_doc_number] => 20050258879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Clock frequency divider and trigger signal generation circuit for same' [patent_app_type] => utility [patent_app_number] => 11/060477 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7777 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258879.pdf [firstpage_image] =>[orig_patent_app_number] => 11060477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 634996 [patent_doc_number] => 07129762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-31 [patent_title] => 'Efficient implementation of a bypassable flip-flop with a clock enable' [patent_app_type] => utility [patent_app_number] => 11/059967 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6553 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129762.pdf [firstpage_image] =>[orig_patent_app_number] => 11059967 [rel_patent_id] =>[rel_patent_doc_number] =>)