Search

Peter T. Brown

Examiner (ID: 10284)

Most Active Art Unit
2508
Art Unit(s)
2811, 2899, 2508, 2822
Total Applications
696
Issued Applications
472
Pending Applications
21
Abandoned Applications
203

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3517651 [patent_doc_number] => 05563614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Low noise dual polarization electromagnetic power reception and conversion system' [patent_app_type] => 1 [patent_app_number] => 8/389723 [patent_app_country] => US [patent_app_date] => 1995-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2809 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563614.pdf [firstpage_image] =>[orig_patent_app_number] => 389723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389723
Low noise dual polarization electromagnetic power reception and conversion system Feb 14, 1995 Issued
Array ( [id] => 3668739 [patent_doc_number] => 05598032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Hybrid chip card capable of both contact and contact-free operation and having antenna contacts situated in a cavity for an electronic module' [patent_app_type] => 1 [patent_app_number] => 8/388102 [patent_app_country] => US [patent_app_date] => 1995-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3247 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598032.pdf [firstpage_image] =>[orig_patent_app_number] => 388102 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/388102
Hybrid chip card capable of both contact and contact-free operation and having antenna contacts situated in a cavity for an electronic module Feb 12, 1995 Issued
08/378742 PROJECTING ELECTRODE STRUCTURE AND PROCESS FOR FORMING SAME Jan 25, 1995 Abandoned
08/376200 SEMICONDUCTOR DEVICE COMPRISING A PLURALITY OF INTERCONNECTION PATTERNS Jan 19, 1995 Abandoned
08/374016 AN INTEGRATED CIRCUIT DEVICE WITH RECORD CROSS TALK Jan 17, 1995 Abandoned
Array ( [id] => 3106420 [patent_doc_number] => 05448106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Thin semiconductor integrated circuit device assembly' [patent_app_type] => 1 [patent_app_number] => 8/373491 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448106.pdf [firstpage_image] =>[orig_patent_app_number] => 373491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/373491
Thin semiconductor integrated circuit device assembly Jan 16, 1995 Issued
08/371126 SEMICONDUCTOR DEVICE HAVING A WIRING FORMED BY SILVER BROMIDE AND METHOD OF MANUFACTURING THE SAME Jan 10, 1995 Abandoned
08/370492 INTEGRATED CIRCUIT STRUCTURE HAVING REDUCED CROSS-TALK AND METHOD OF MAKING SAME Jan 8, 1995 Abandoned
Array ( [id] => 3961408 [patent_doc_number] => 05936306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'TiSi.sub.2 /TiN clad interconnect technology' [patent_app_type] => 1 [patent_app_number] => 8/369562 [patent_app_country] => US [patent_app_date] => 1995-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1746 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936306.pdf [firstpage_image] =>[orig_patent_app_number] => 369562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/369562
TiSi.sub.2 /TiN clad interconnect technology Jan 5, 1995 Issued
Array ( [id] => 3427601 [patent_doc_number] => 05459353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Semiconductor device including interlayer dielectric film layers and conductive film layers' [patent_app_type] => 1 [patent_app_number] => 8/369253 [patent_app_country] => US [patent_app_date] => 1995-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 11744 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459353.pdf [firstpage_image] =>[orig_patent_app_number] => 369253 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/369253
Semiconductor device including interlayer dielectric film layers and conductive film layers Jan 4, 1995 Issued
Array ( [id] => 3561642 [patent_doc_number] => 05502324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Composite wiring layer' [patent_app_type] => 1 [patent_app_number] => 8/363548 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 3473 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502324.pdf [firstpage_image] =>[orig_patent_app_number] => 363548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/363548
Composite wiring layer Dec 22, 1994 Issued
08/358259 LOW LOSS ELECTROMAGNETIC ENERGY PROBE Dec 18, 1994 Abandoned
Array ( [id] => 3548680 [patent_doc_number] => 05554878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Intergrated high-voltage resistor including field-plate layers' [patent_app_type] => 1 [patent_app_number] => 8/352425 [patent_app_country] => US [patent_app_date] => 1994-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1547 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/554/05554878.pdf [firstpage_image] =>[orig_patent_app_number] => 352425 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352425
Intergrated high-voltage resistor including field-plate layers Dec 7, 1994 Issued
Array ( [id] => 3491877 [patent_doc_number] => 05475267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Multilayer interconnection structure for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/354737 [patent_app_country] => US [patent_app_date] => 1994-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5865 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475267.pdf [firstpage_image] =>[orig_patent_app_number] => 354737 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354737
Multilayer interconnection structure for a semiconductor device Dec 7, 1994 Issued
Array ( [id] => 3626683 [patent_doc_number] => 05594271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Load current detecting device including a multi-emitter bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/354085 [patent_app_country] => US [patent_app_date] => 1994-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2485 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594271.pdf [firstpage_image] =>[orig_patent_app_number] => 354085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354085
Load current detecting device including a multi-emitter bipolar transistor Dec 5, 1994 Issued
Array ( [id] => 3594391 [patent_doc_number] => 05585673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Refractory metal capped low resistivity metal conductor lines and vias' [patent_app_type] => 1 [patent_app_number] => 8/346208 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 6674 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585673.pdf [firstpage_image] =>[orig_patent_app_number] => 346208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/346208
Refractory metal capped low resistivity metal conductor lines and vias Nov 21, 1994 Issued
Array ( [id] => 3476391 [patent_doc_number] => 05477087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Bump electrode for connecting electronic components' [patent_app_type] => 1 [patent_app_number] => 8/341842 [patent_app_country] => US [patent_app_date] => 1994-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 3320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477087.pdf [firstpage_image] =>[orig_patent_app_number] => 341842 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341842
Bump electrode for connecting electronic components Nov 17, 1994 Issued
Array ( [id] => 3427508 [patent_doc_number] => 05459346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Semiconductor substrate with electrical contact in groove' [patent_app_type] => 1 [patent_app_number] => 8/341265 [patent_app_country] => US [patent_app_date] => 1994-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 6198 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459346.pdf [firstpage_image] =>[orig_patent_app_number] => 341265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341265
Semiconductor substrate with electrical contact in groove Nov 16, 1994 Issued
Array ( [id] => 3457159 [patent_doc_number] => 05451804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'VLSI device with global planarization' [patent_app_type] => 1 [patent_app_number] => 8/342020 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2811 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451804.pdf [firstpage_image] =>[orig_patent_app_number] => 342020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/342020
VLSI device with global planarization Nov 15, 1994 Issued
Array ( [id] => 3554660 [patent_doc_number] => 05572072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Semiconductor device having a multi-layer metallization structure' [patent_app_type] => 1 [patent_app_number] => 8/341982 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 30 [patent_no_of_words] => 12241 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572072.pdf [firstpage_image] =>[orig_patent_app_number] => 341982 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341982
Semiconductor device having a multi-layer metallization structure Nov 15, 1994 Issued
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