Search

Peter T. Di Mauro

Examiner (ID: 862)

Most Active Art Unit
1103
Art Unit(s)
1103, 1754, 1709
Total Applications
371
Issued Applications
226
Pending Applications
40
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5246265 [patent_doc_number] => 20070242499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TRIMMING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/697059 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7507 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242499.pdf [firstpage_image] =>[orig_patent_app_number] => 11697059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697059
Semiconductor integrated circuit device and trimming method of semiconductor integrated circuit device Apr 4, 2007 Issued
Array ( [id] => 4680278 [patent_doc_number] => 20080246504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'APPARATUS AND METHOD TO MANAGE EXTERNAL VOLTAGE FOR SEMICONDUCTOR MEMORY TESTING WITH SERIAL INTERFACE' [patent_app_type] => utility [patent_app_number] => 11/696521 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4747 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20080246504.pdf [firstpage_image] =>[orig_patent_app_number] => 11696521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/696521
Apparatus and method to manage external voltage for semiconductor memory testing with serial interface Apr 3, 2007 Issued
Array ( [id] => 804710 [patent_doc_number] => 07423913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Structures and methods for enhancing erase uniformity in a nitride read-only memory array' [patent_app_type] => utility [patent_app_number] => 11/695668 [patent_app_country] => US [patent_app_date] => 2007-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4693 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/423/07423913.pdf [firstpage_image] =>[orig_patent_app_number] => 11695668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695668
Structures and methods for enhancing erase uniformity in a nitride read-only memory array Apr 2, 2007 Issued
Array ( [id] => 586046 [patent_doc_number] => 07460426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/727915 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4685 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/460/07460426.pdf [firstpage_image] =>[orig_patent_app_number] => 11727915 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727915
Semiconductor memory device Mar 28, 2007 Issued
Array ( [id] => 5246293 [patent_doc_number] => 20070242527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE FOR STORING MULTILEVEL DATA' [patent_app_type] => utility [patent_app_number] => 11/693213 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13873 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242527.pdf [firstpage_image] =>[orig_patent_app_number] => 11693213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693213
Semiconductor memory device for storing multilevel data Mar 28, 2007 Issued
Array ( [id] => 349853 [patent_doc_number] => 07495977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-24 [patent_title] => 'Memory system having high-speed row block and column redundancy' [patent_app_type] => utility [patent_app_number] => 11/731605 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4184 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495977.pdf [firstpage_image] =>[orig_patent_app_number] => 11731605 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731605
Memory system having high-speed row block and column redundancy Mar 28, 2007 Issued
Array ( [id] => 5124714 [patent_doc_number] => 20070236985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/692501 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 20435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236985.pdf [firstpage_image] =>[orig_patent_app_number] => 11692501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692501
Semiconductor memory device Mar 27, 2007 Issued
Array ( [id] => 4738533 [patent_doc_number] => 20080232185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Structure and Method of Implementing Power Savings During Addressing of DRAM Architectures' [patent_app_type] => utility [patent_app_number] => 11/688897 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232185.pdf [firstpage_image] =>[orig_patent_app_number] => 11688897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688897
Structure and method of implementing power savings during addressing of DRAM architectures Mar 20, 2007 Issued
Array ( [id] => 5257883 [patent_doc_number] => 20070211515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Resistive Memory Arrangement' [patent_app_type] => utility [patent_app_number] => 11/688556 [patent_app_country] => US [patent_app_date] => 2007-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20070211515.pdf [firstpage_image] =>[orig_patent_app_number] => 11688556 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688556
Resistive memory arrangement Mar 19, 2007 Issued
Array ( [id] => 4976026 [patent_doc_number] => 20070217257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'SYNCHRONIZATION OF READ AND VERIFY OPERATIONS THAT MAY BE CARRIED OUT AT THE SAME TIME OVER DISTINCT PARTITIONS OF A FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 11/686133 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2276 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217257.pdf [firstpage_image] =>[orig_patent_app_number] => 11686133 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/686133
Synchronization of operations in distinct memory partitions Mar 13, 2007 Issued
Array ( [id] => 4931732 [patent_doc_number] => 20080002507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'ROW ADDRESS CONTROLLER' [patent_app_type] => utility [patent_app_number] => 11/683609 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7116 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002507.pdf [firstpage_image] =>[orig_patent_app_number] => 11683609 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683609
Row address controller Mar 7, 2007 Issued
Array ( [id] => 367513 [patent_doc_number] => 07480198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Semiconductor memory device and driving method of semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/680999 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480198.pdf [firstpage_image] =>[orig_patent_app_number] => 11680999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680999
Semiconductor memory device and driving method of semiconductor memory device Feb 28, 2007 Issued
Array ( [id] => 5003723 [patent_doc_number] => 20070201290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'SENSE AMPLIFIER CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/677623 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4412 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201290.pdf [firstpage_image] =>[orig_patent_app_number] => 11677623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677623
Sense amplifier circuit in semiconductor memory device and driving method thereof Feb 21, 2007 Issued
Array ( [id] => 5003704 [patent_doc_number] => 20070201271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'MEMORY DEVICE WITH HIERARCHY BIT LINE' [patent_app_type] => utility [patent_app_number] => 11/677633 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201271.pdf [firstpage_image] =>[orig_patent_app_number] => 11677633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677633
Memory device with hierarchy bit line Feb 21, 2007 Issued
Array ( [id] => 5003693 [patent_doc_number] => 20070201260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'MEMORY DEVICE WITH HIERARCHY BIT LINE' [patent_app_type] => utility [patent_app_number] => 11/677630 [patent_app_country] => US [patent_app_date] => 2007-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2567 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20070201260.pdf [firstpage_image] =>[orig_patent_app_number] => 11677630 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/677630
Memory device with hierarchy bit line Feb 21, 2007 Issued
Array ( [id] => 5021186 [patent_doc_number] => 20070147152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Sense amplifier for semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/706409 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9069 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147152.pdf [firstpage_image] =>[orig_patent_app_number] => 11706409 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706409
Sense amplifier for semiconductor memory device Feb 14, 2007 Issued
Array ( [id] => 815055 [patent_doc_number] => 07414905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Semiconductor integrated circuit and testing method therefor' [patent_app_type] => utility [patent_app_number] => 11/674511 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414905.pdf [firstpage_image] =>[orig_patent_app_number] => 11674511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674511
Semiconductor integrated circuit and testing method therefor Feb 12, 2007 Issued
Array ( [id] => 815062 [patent_doc_number] => 07414911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Cascade wake-up circuit preventing power noise in memory device' [patent_app_type] => utility [patent_app_number] => 11/704089 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4999 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/414/07414911.pdf [firstpage_image] =>[orig_patent_app_number] => 11704089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704089
Cascade wake-up circuit preventing power noise in memory device Feb 7, 2007 Issued
Array ( [id] => 564643 [patent_doc_number] => 07468925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Semiconductor memory device realizing high-speed access' [patent_app_type] => utility [patent_app_number] => 11/703785 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4581 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/468/07468925.pdf [firstpage_image] =>[orig_patent_app_number] => 11703785 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703785
Semiconductor memory device realizing high-speed access Feb 7, 2007 Issued
Array ( [id] => 5251826 [patent_doc_number] => 20070133282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Nonvolatile Semiconductor Memory' [patent_app_type] => utility [patent_app_number] => 11/671190 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 33297 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133282.pdf [firstpage_image] =>[orig_patent_app_number] => 11671190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671190
Nonvolatile semiconductor memory Feb 4, 2007 Issued
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