Search

Phallaka Kik

Examiner (ID: 18158)

Most Active Art Unit
2851
Art Unit(s)
2851, 2763, 2764, 2304, 2825, 2768
Total Applications
1948
Issued Applications
1741
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19660912 [patent_doc_number] => 20240427977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => QUICK SIMULATION AND OPTIMIZATION METHOD AND SYSTEM FOR ANALOG CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/823587 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 504 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823587
Quick simulation and optimization method and system for analog circuits Sep 2, 2024 Issued
Array ( [id] => 19434908 [patent_doc_number] => 20240303406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 18/665300 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665300
CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES May 14, 2024 Pending
Array ( [id] => 19434908 [patent_doc_number] => 20240303406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 18/665300 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665300
CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES May 14, 2024 Pending
Array ( [id] => 19332007 [patent_doc_number] => 20240246437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SYSTEMS AND MOBILE APPLICATION FOR ELECTRIC WIRELESS CHARGING STATIONS [patent_app_type] => utility [patent_app_number] => 18/625700 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625700
SYSTEMS AND MOBILE APPLICATION FOR ELECTRIC WIRELESS CHARGING STATIONS Apr 2, 2024 Pending
Array ( [id] => 19857322 [patent_doc_number] => 12260160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Fabricated layout correlation [patent_app_type] => utility [patent_app_number] => 18/408018 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408018
Fabricated layout correlation Jan 8, 2024 Issued
Array ( [id] => 19174848 [patent_doc_number] => 20240160822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/539238 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539238
System and method for using interface protection parameters Dec 12, 2023 Issued
Array ( [id] => 19174848 [patent_doc_number] => 20240160822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/539238 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539238
System and method for using interface protection parameters Dec 12, 2023 Issued
Array ( [id] => 19008502 [patent_doc_number] => 20240072573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Wireless Power System With Voltage Regulation [patent_app_type] => utility [patent_app_number] => 18/503389 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503389
Wireless power system with voltage regulation Nov 6, 2023 Issued
Array ( [id] => 19719450 [patent_doc_number] => 12204990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Error corrected variational algorithms [patent_app_type] => utility [patent_app_number] => 18/499879 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499879
Error corrected variational algorithms Oct 31, 2023 Issued
Array ( [id] => 18897490 [patent_doc_number] => 20240012975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => LOGIC CELL STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/472280 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472280
Logic cell structures and related methods Sep 21, 2023 Issued
Array ( [id] => 19304018 [patent_doc_number] => 20240232598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => GENERAL PADDING SUPPORT FOR CONVOLUTION ON SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 18/469272 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/469272
General padding support for convolution on systolic arrays Sep 17, 2023 Issued
Array ( [id] => 18832843 [patent_doc_number] => 20230401370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/446739 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446739
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT DESIGN Aug 8, 2023 Pending
Array ( [id] => 18896852 [patent_doc_number] => 20240012337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD OF DETERMINING CONTROL PARAMETERS OF A DEVICE MANUFACTURING PROCESS [patent_app_type] => utility [patent_app_number] => 18/229984 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229984
Method of determining control parameters of a device manufacturing process Aug 2, 2023 Issued
Array ( [id] => 19669736 [patent_doc_number] => 12182488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Semiconductor device including standard-cell-adapted power grid arrangement [patent_app_type] => utility [patent_app_number] => 18/362839 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362839
Semiconductor device including standard-cell-adapted power grid arrangement Jul 30, 2023 Issued
Array ( [id] => 19942512 [patent_doc_number] => 12314644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Integrated circuit design method, system and computer program product [patent_app_type] => utility [patent_app_number] => 18/356426 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356426
Integrated circuit design method, system and computer program product Jul 20, 2023 Issued
Array ( [id] => 19115220 [patent_doc_number] => 20240126970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/341495 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341495 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341495
Integrated circuit design system and method Jun 25, 2023 Issued
Array ( [id] => 18651644 [patent_doc_number] => 20230297480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other [patent_app_type] => utility [patent_app_number] => 18/323931 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323931
Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other May 24, 2023 Pending
Array ( [id] => 18599258 [patent_doc_number] => 20230274058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => AUTOMATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 18/314012 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314012
Automated circuit generation May 7, 2023 Issued
Array ( [id] => 19228659 [patent_doc_number] => 12008296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Automated circuit generation [patent_app_type] => utility [patent_app_number] => 18/314000 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 110 [patent_no_of_words] => 64608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314000 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314000
Automated circuit generation May 7, 2023 Issued
Array ( [id] => 19443351 [patent_doc_number] => 12093619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Automated circuit generation [patent_app_type] => utility [patent_app_number] => 18/314029 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 110 [patent_no_of_words] => 64670 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314029
Automated circuit generation May 7, 2023 Issued
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