Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18104545 [patent_doc_number] => 11544435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => On-the-fly computation of analog mixed-signal (AMS) measurements [patent_app_type] => utility [patent_app_number] => 17/353208 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 14186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353208
On-the-fly computation of analog mixed-signal (AMS) measurements Jun 20, 2021 Issued
Array ( [id] => 18119585 [patent_doc_number] => 11550980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-10 [patent_title] => System and method for generating power-aware electronics [patent_app_type] => utility [patent_app_number] => 17/346929 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346929
System and method for generating power-aware electronics Jun 13, 2021 Issued
Array ( [id] => 18547380 [patent_doc_number] => 11720733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Integrated circuit design system and method [patent_app_type] => utility [patent_app_number] => 17/340825 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340825
Integrated circuit design system and method Jun 6, 2021 Issued
Array ( [id] => 18006370 [patent_doc_number] => 20220365136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND SYSTEM FOR EFFICIENT TESTING OF DIGITAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/319835 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319835
Method and system for efficient testing of digital integrated circuits May 12, 2021 Issued
Array ( [id] => 17216715 [patent_doc_number] => 20210350053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => DETERMINING AND VERIFYING METASTABILITY IN CLOCK DOMAIN CROSSINGS [patent_app_type] => utility [patent_app_number] => 17/316610 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316610
Determining and verifying metastability in clock domain crossings May 9, 2021 Issued
Array ( [id] => 18291558 [patent_doc_number] => 11620428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-04 [patent_title] => Post-CTS clock tree restructuring [patent_app_type] => utility [patent_app_number] => 17/315019 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315019
Post-CTS clock tree restructuring May 6, 2021 Issued
Array ( [id] => 17651749 [patent_doc_number] => 11354479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Post-CTS clock tree restructuring with ripple move [patent_app_type] => utility [patent_app_number] => 17/315032 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315032
Post-CTS clock tree restructuring with ripple move May 6, 2021 Issued
Array ( [id] => 18913391 [patent_doc_number] => 11876383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-16 [patent_title] => Wireless power system with voltage regulation [patent_app_type] => utility [patent_app_number] => 17/313589 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313589
Wireless power system with voltage regulation May 5, 2021 Issued
Array ( [id] => 17038589 [patent_doc_number] => 20210255548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => PROCESS VARIABILITY AWARE ADAPTIVE INSPECTION AND METROLOGY [patent_app_type] => utility [patent_app_number] => 17/313135 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/313135
Process variability aware adaptive inspection and metrology May 5, 2021 Issued
Array ( [id] => 17026031 [patent_doc_number] => 20210249903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => WIRELESSLY CHARGEABLE BATTERY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/244964 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244964
Wirelessly chargeable battery apparatus Apr 29, 2021 Issued
Array ( [id] => 18072964 [patent_doc_number] => 11531798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Methods and apparatus to simulate metastability for circuit design verification [patent_app_type] => utility [patent_app_number] => 17/246136 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 13969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246136
Methods and apparatus to simulate metastability for circuit design verification Apr 29, 2021 Issued
Array ( [id] => 17606208 [patent_doc_number] => 11334698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Cell-aware defect characterization by considering inter-cell timing [patent_app_type] => utility [patent_app_number] => 17/244126 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244126
Cell-aware defect characterization by considering inter-cell timing Apr 28, 2021 Issued
Array ( [id] => 18430725 [patent_doc_number] => 11675947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Multidimensional FPGA virtualization [patent_app_type] => utility [patent_app_number] => 17/240052 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/240052
Multidimensional FPGA virtualization Apr 25, 2021 Issued
Array ( [id] => 17269518 [patent_doc_number] => 11194945 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-07 [patent_title] => Clock deadlock detecting system, method, and non-transitory computer readable storage medium [patent_app_type] => utility [patent_app_number] => 17/236193 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236193
Clock deadlock detecting system, method, and non-transitory computer readable storage medium Apr 20, 2021 Issued
Array ( [id] => 17948172 [patent_doc_number] => 20220335191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => LOGIC CELL STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/232525 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232525
Logic cell structures and related methods Apr 15, 2021 Issued
Array ( [id] => 17423381 [patent_doc_number] => 11256839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-22 [patent_title] => IP block scan chain construction [patent_app_type] => utility [patent_app_number] => 17/228282 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/228282
IP block scan chain construction Apr 11, 2021 Issued
Array ( [id] => 16980213 [patent_doc_number] => 20210224450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory [patent_app_type] => utility [patent_app_number] => 17/221535 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/221535
Address generators for verifying integrated circuit hardware designs for cache memory Apr 1, 2021 Issued
Array ( [id] => 17438042 [patent_doc_number] => 11263377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Circuit architecture for expanded design for testability functionality [patent_app_type] => utility [patent_app_number] => 17/219174 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219174
Circuit architecture for expanded design for testability functionality Mar 30, 2021 Issued
Array ( [id] => 18053265 [patent_doc_number] => 11526650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Switching power aware driver resizing by considering net activity in buffering algorithm [patent_app_type] => utility [patent_app_number] => 17/219761 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219761 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219761
Switching power aware driver resizing by considering net activity in buffering algorithm Mar 30, 2021 Issued
Array ( [id] => 17409304 [patent_doc_number] => 11250191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Offline functional coverage collection [patent_app_type] => utility [patent_app_number] => 17/301289 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301289
Offline functional coverage collection Mar 29, 2021 Issued
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