Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17380189 [patent_doc_number] => 11238206 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Partition wire assignment for routing multi-partition circuit designs [patent_app_type] => utility [patent_app_number] => 17/213474 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 12425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213474
Partition wire assignment for routing multi-partition circuit designs Mar 25, 2021 Issued
Array ( [id] => 17977678 [patent_doc_number] => 11494540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Method, system, and computer program product for implementing electronic design closure with reduction techniques [patent_app_type] => utility [patent_app_number] => 17/214716 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214716
Method, system, and computer program product for implementing electronic design closure with reduction techniques Mar 25, 2021 Issued
Array ( [id] => 18513608 [patent_doc_number] => 20230229843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => PCB METAL BALANCING [patent_app_type] => utility [patent_app_number] => 17/914579 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/914579
PCB METAL BALANCING Mar 24, 2021 Pending
Array ( [id] => 18513608 [patent_doc_number] => 20230229843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => PCB METAL BALANCING [patent_app_type] => utility [patent_app_number] => 17/914579 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/914579
PCB METAL BALANCING Mar 24, 2021 Pending
Array ( [id] => 16918186 [patent_doc_number] => 20210191278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => COMPUTATIONAL METROLOGY [patent_app_type] => utility [patent_app_number] => 17/197167 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197167
Computational metrology Mar 9, 2021 Issued
Array ( [id] => 16950591 [patent_doc_number] => 20210209283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING STANDARD-CELL-ADAPTED POWER GRID ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/195094 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195094
Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement Mar 7, 2021 Issued
Array ( [id] => 18720389 [patent_doc_number] => 11797735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => Regression testing based on overall confidence estimating [patent_app_type] => utility [patent_app_number] => 17/194147 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17194147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/194147
Regression testing based on overall confidence estimating Mar 4, 2021 Issued
Array ( [id] => 19293535 [patent_doc_number] => 12032889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Fast effective resistance estimation using machine learning regression algorithms [patent_app_type] => utility [patent_app_number] => 17/190336 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190336
Fast effective resistance estimation using machine learning regression algorithms Mar 1, 2021 Issued
Array ( [id] => 16982223 [patent_doc_number] => 20210226460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => Modular Charging System and Wall-Mounted Charging Device and Modular Power Devices [patent_app_type] => utility [patent_app_number] => 17/180750 [patent_app_country] => US [patent_app_date] => 2021-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180750
Modular charging system and wall-mounted charging device and modular power devices Feb 19, 2021 Issued
Array ( [id] => 16887799 [patent_doc_number] => 20210173996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/179014 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179014
Method and layout of an integrated circuit Feb 17, 2021 Issued
Array ( [id] => 17352452 [patent_doc_number] => 11227091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Physical failure analysis-oriented diagnosis resolution prediction [patent_app_type] => utility [patent_app_number] => 17/175011 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17175011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/175011
Physical failure analysis-oriented diagnosis resolution prediction Feb 11, 2021 Issued
Array ( [id] => 18278430 [patent_doc_number] => 20230093902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => METHOD AND DEVICE FOR INCREASING ENERGY DENSITY [patent_app_type] => utility [patent_app_number] => 17/799537 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/799537
Method and device for increasing energy density Feb 10, 2021 Issued
Array ( [id] => 17606212 [patent_doc_number] => 11334702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => Mixed-signal simulation for complex design topologies [patent_app_type] => utility [patent_app_number] => 17/173963 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173963
Mixed-signal simulation for complex design topologies Feb 10, 2021 Issued
Array ( [id] => 17552233 [patent_doc_number] => 20220123576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD FOR MANAGING CHARGING AND DISCHARGING OF PARALLEL-CONNECTED BATTERY PACK, ELECTRONIC DEVICE, AND ELECTRICAL SYSTEM [patent_app_type] => utility [patent_app_number] => 17/281667 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17281667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/281667
Method for managing charging and discharging of parallel-connected battery pack, electronic device, and electrical system Feb 8, 2021 Issued
Array ( [id] => 18223488 [patent_doc_number] => 20230062482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Systems, Devices, and Methods for Dedicated Low Temperature Design and Operation [patent_app_type] => utility [patent_app_number] => 17/798518 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17798518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/798518
Systems, Devices, and Methods for Dedicated Low Temperature Design and Operation Feb 7, 2021 Pending
Array ( [id] => 17621530 [patent_doc_number] => 11340584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Synchronized parallel tile computation for large area lithography simulation [patent_app_type] => utility [patent_app_number] => 17/170389 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 13724 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170389
Synchronized parallel tile computation for large area lithography simulation Feb 7, 2021 Issued
Array ( [id] => 16854360 [patent_doc_number] => 20210155105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => CORD REEL VARIABLE CURRENT THERMAL MANAGEMENT AND DAMAGE DETECTION [patent_app_type] => utility [patent_app_number] => 17/165532 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165532
Cord reel variable current thermal management and damage detection Feb 1, 2021 Issued
Array ( [id] => 17009744 [patent_doc_number] => 20210240905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => ADVANCED CELL-AWARE FAULT MODEL FOR YIELD ANALYSIS AND PHYSICAL FAILURE ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/159017 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159017
Advanced cell-aware fault model for yield analysis and physical failure analysis Jan 25, 2021 Issued
Array ( [id] => 16887790 [patent_doc_number] => 20210173987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => RESET CROSSING AND CLOCK CROSSING INTERFACE FOR INTEGRATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 17/157564 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157564
Reset crossing and clock crossing interface for integrated circuit generation Jan 24, 2021 Issued
Array ( [id] => 16982219 [patent_doc_number] => 20210226456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => POWER STORAGE DEVICE CONTROL SYSTEM, POWER STORAGE SYSTEM, AND ELECTRICAL APPLIANCE [patent_app_type] => utility [patent_app_number] => 17/149779 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149779
Power storage device control system, power storage system, and electrical appliance Jan 14, 2021 Issued
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