Search

Phallaka Kik

Examiner (ID: 18158)

Most Active Art Unit
2851
Art Unit(s)
2851, 2763, 2764, 2304, 2825, 2768
Total Applications
1948
Issued Applications
1741
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17253204 [patent_doc_number] => 11188697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-30 [patent_title] => On-chip memory access pattern detection for power and resource reduction [patent_app_type] => utility [patent_app_number] => 17/141983 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10555 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141983
On-chip memory access pattern detection for power and resource reduction Jan 4, 2021 Issued
Array ( [id] => 18174112 [patent_doc_number] => 11573822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => System and method for generating and using a context block based on system parameters [patent_app_type] => utility [patent_app_number] => 17/137365 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137365
System and method for generating and using a context block based on system parameters Dec 29, 2020 Issued
Array ( [id] => 17824825 [patent_doc_number] => 11429773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Methods, systems, and computer program product for implementing an electronic design using connect modules with dynamic and interactive control [patent_app_type] => utility [patent_app_number] => 17/138853 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17138853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/138853
Methods, systems, and computer program product for implementing an electronic design using connect modules with dynamic and interactive control Dec 29, 2020 Issued
Array ( [id] => 17528925 [patent_doc_number] => 11301614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Feasibility analysis of engineering change orders [patent_app_type] => utility [patent_app_number] => 17/132257 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17132257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/132257
Feasibility analysis of engineering change orders Dec 22, 2020 Issued
Array ( [id] => 18161090 [patent_doc_number] => 20230027682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => SYSTEMS AND METHODS FOR TUNING CAPACITANCE OF QUBITS [patent_app_type] => utility [patent_app_number] => 17/786192 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -51 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17786192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/786192
SYSTEMS AND METHODS FOR TUNING CAPACITANCE OF QUBITS Dec 14, 2020 Pending
Array ( [id] => 17581530 [patent_doc_number] => 20220138385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => INTEGRATED CIRCUIT DESIGN METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 17/122769 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122769
Integrated circuit design method, system and computer program product Dec 14, 2020 Issued
Array ( [id] => 17202634 [patent_doc_number] => 20210342729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => Modular Quantum Processor Architectures [patent_app_type] => utility [patent_app_number] => 17/119089 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119089
Modular quantum processor architectures Dec 10, 2020 Issued
Array ( [id] => 16903546 [patent_doc_number] => 20210182462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SYSTEM-ON-CHIP AUTOMATIC DESIGN DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/116637 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116637
System-on-chip automatic design device and operation method thereof Dec 8, 2020 Issued
Array ( [id] => 17309329 [patent_doc_number] => 11210445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => System and method for interface protection [patent_app_type] => utility [patent_app_number] => 17/116242 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116242
System and method for interface protection Dec 8, 2020 Issued
Array ( [id] => 16724429 [patent_doc_number] => 20210091576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Battery Control System and Method, and Electronic Device [patent_app_type] => utility [patent_app_number] => 17/110967 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110967
Battery control system and method, and electronic device Dec 2, 2020 Issued
Array ( [id] => 17380190 [patent_doc_number] => 11238207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Method and system for fabricating integrated circuit with aid of programmable circuit synthesis [patent_app_type] => utility [patent_app_number] => 17/103724 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103724
Method and system for fabricating integrated circuit with aid of programmable circuit synthesis Nov 23, 2020 Issued
Array ( [id] => 17136798 [patent_doc_number] => 11138355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Unreachable cover root cause search [patent_app_type] => utility [patent_app_number] => 17/099301 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099301 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099301
Unreachable cover root cause search Nov 15, 2020 Issued
Array ( [id] => 17499729 [patent_doc_number] => 11288435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Failure analysis apparatus, computer readable recording medium and failure analysis method [patent_app_type] => utility [patent_app_number] => 17/097896 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7057 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097896
Failure analysis apparatus, computer readable recording medium and failure analysis method Nov 12, 2020 Issued
Array ( [id] => 16810301 [patent_doc_number] => 20210132856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => APPARATUS AND ARCHITETURE OF NON-VOLATILE MEMORY MODULE IN PARALLEL CONFIGURATION [patent_app_type] => utility [patent_app_number] => 17/094787 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094787
Apparatus and architecture of non-volatile memory module in parallel configuration Nov 9, 2020 Issued
Array ( [id] => 17824821 [patent_doc_number] => 11429769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Implementing a hardware description language memory using heterogeneous memory primitives [patent_app_type] => utility [patent_app_number] => 17/085838 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 12017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085838
Implementing a hardware description language memory using heterogeneous memory primitives Oct 29, 2020 Issued
Array ( [id] => 19167696 [patent_doc_number] => 11983605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Partitioned template matching and symbolic peephole optimization [patent_app_type] => utility [patent_app_number] => 17/082844 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082844
Partitioned template matching and symbolic peephole optimization Oct 27, 2020 Issued
Array ( [id] => 16849367 [patent_doc_number] => 20210150112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Layout-Friendly Test Pattern Decompressor [patent_app_type] => utility [patent_app_number] => 17/082462 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17082462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/082462
Layout-friendly test pattern decompressor Oct 27, 2020 Issued
Array ( [id] => 16659612 [patent_doc_number] => 20210056249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => ENGINEERING CHANGE ORDER CELL STRUCTURE HAVING ALWAYS-ON TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/081438 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081438
Engineering change order cell structure having always-on transistor Oct 26, 2020 Issued
Array ( [id] => 17001638 [patent_doc_number] => 11080450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => Calculating inductance based on a netlist [patent_app_type] => utility [patent_app_number] => 17/071848 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071848
Calculating inductance based on a netlist Oct 14, 2020 Issued
Array ( [id] => 17499726 [patent_doc_number] => 11288432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Computer implemented system and method for generating a layout of a cell defining a circuit component [patent_app_type] => utility [patent_app_number] => 17/062567 [patent_app_country] => US [patent_app_date] => 2020-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 62 [patent_no_of_words] => 32513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062567
Computer implemented system and method for generating a layout of a cell defining a circuit component Oct 2, 2020 Issued
Menu