Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17499726 [patent_doc_number] => 11288432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Computer implemented system and method for generating a layout of a cell defining a circuit component [patent_app_type] => utility [patent_app_number] => 17/062567 [patent_app_country] => US [patent_app_date] => 2020-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 62 [patent_no_of_words] => 32513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062567
Computer implemented system and method for generating a layout of a cell defining a circuit component Oct 2, 2020 Issued
Array ( [id] => 17121348 [patent_doc_number] => 11132484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-28 [patent_title] => Controlling clocks and resets in a logic built in self-test [patent_app_type] => utility [patent_app_number] => 17/062182 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062182
Controlling clocks and resets in a logic built in self-test Oct 1, 2020 Issued
Array ( [id] => 17606214 [patent_doc_number] => 11334704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => System, method, and computer program product for mixed signal verification [patent_app_type] => utility [patent_app_number] => 17/060263 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17060263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/060263
System, method, and computer program product for mixed signal verification Sep 30, 2020 Issued
Array ( [id] => 16834265 [patent_doc_number] => 11010520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-18 [patent_title] => System and method for circuit synthesis using partial boolean quantification [patent_app_type] => utility [patent_app_number] => 17/037122 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037122
System and method for circuit synthesis using partial boolean quantification Sep 28, 2020 Issued
Array ( [id] => 16730076 [patent_doc_number] => 20210097223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHODS AND SYSTEMS FOR FACILITATING DESIGNING A PROGRAMMABLE LOGIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/035326 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035326
Methods and systems for facilitating designing a programmable logic device Sep 27, 2020 Issued
Array ( [id] => 16577650 [patent_doc_number] => 20210012051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => CIRCUIT DESIGN VISIBILITY IN INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 17/033208 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033208
Circuit design visibility in integrated circuit devices Sep 24, 2020 Issued
Array ( [id] => 16559368 [patent_doc_number] => 20210004517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHOD OF DESIGNING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/029985 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029985
Method of designing semiconductor device Sep 22, 2020 Issued
Array ( [id] => 17492523 [patent_doc_number] => 11281828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-22 [patent_title] => Automated analog layout [patent_app_type] => utility [patent_app_number] => 17/028937 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 45 [patent_no_of_words] => 15988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028937
Automated analog layout Sep 21, 2020 Issued
Array ( [id] => 17017424 [patent_doc_number] => 11087066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Static voltage drop (SIR) violation prediction systems and methods [patent_app_type] => utility [patent_app_number] => 17/027370 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 13111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027370
Static voltage drop (SIR) violation prediction systems and methods Sep 20, 2020 Issued
Array ( [id] => 16559369 [patent_doc_number] => 20210004518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => METHOD FOR IMPROVED CUT METAL PATTERNING [patent_app_type] => utility [patent_app_number] => 17/027023 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027023
Method for improved cut metal patterning Sep 20, 2020 Issued
Array ( [id] => 17151619 [patent_doc_number] => 11144697 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => Processing method for applying analog dynamic circuit to digital testing tool [patent_app_type] => utility [patent_app_number] => 17/020868 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2879 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020868
Processing method for applying analog dynamic circuit to digital testing tool Sep 14, 2020 Issued
Array ( [id] => 16542135 [patent_doc_number] => 20200408549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => SYSTEM FOR PROMOTING LENDING OR BORROWING OF PORTABLE ELECTRIC POWER SUPPLY [patent_app_type] => utility [patent_app_number] => 17/021039 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021039
SYSTEM FOR PROMOTING LENDING OR BORROWING OF PORTABLE ELECTRIC POWER SUPPLY Sep 14, 2020 Pending
Array ( [id] => 16788293 [patent_doc_number] => 10990727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Method for radiation hardening of integrated circuits [patent_app_type] => utility [patent_app_number] => 17/016816 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016816 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/016816
Method for radiation hardening of integrated circuits Sep 9, 2020 Issued
Array ( [id] => 17757548 [patent_doc_number] => 11397841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method [patent_app_type] => utility [patent_app_number] => 17/011116 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12226 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011116 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011116
Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method Sep 2, 2020 Issued
Array ( [id] => 17099135 [patent_doc_number] => 20210286926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT DESIGNING APPARATUS, AND CIRCUIT DESIGNING METHOD [patent_app_type] => utility [patent_app_number] => 17/011166 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011166
Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method Sep 2, 2020 Issued
Array ( [id] => 17918493 [patent_doc_number] => 20220320889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => CONTROL CIRCUIT AND POWER SOURCE DEVICE [patent_app_type] => utility [patent_app_number] => 17/642232 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17642232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/642232
Control circuit and power source device Sep 2, 2020 Issued
Array ( [id] => 16845052 [patent_doc_number] => 11017142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Methods and apparatuses of configurable integrated circuits [patent_app_type] => utility [patent_app_number] => 17/010630 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010630
Methods and apparatuses of configurable integrated circuits Sep 1, 2020 Issued
Array ( [id] => 18660165 [patent_doc_number] => 20230306172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => DYNAMIC CDC VERIFICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/023819 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18023819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/023819
DYNAMIC CDC VERIFICATION METHOD Aug 30, 2020 Pending
Array ( [id] => 16910636 [patent_doc_number] => 11042679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-22 [patent_title] => Diagnosis resolution prediction [patent_app_type] => utility [patent_app_number] => 17/007670 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007670 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007670
Diagnosis resolution prediction Aug 30, 2020 Issued
Array ( [id] => 16849366 [patent_doc_number] => 20210150111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => DIAGNOSTIC RESOLUTION ENHANCEMENT WITH REVERSIBLE SCAN CHAINS [patent_app_type] => utility [patent_app_number] => 17/003138 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003138
Diagnostic resolution enhancement with reversible scan chains Aug 25, 2020 Issued
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