Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17802361 [patent_doc_number] => 11416662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-16 [patent_title] => Estimating diagnostic coverage in IC design based on static COI analysis of gate-level netlist and RTL fault simulation [patent_app_type] => utility [patent_app_number] => 16/737257 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737257
Estimating diagnostic coverage in IC design based on static COI analysis of gate-level netlist and RTL fault simulation Jan 7, 2020 Issued
Array ( [id] => 16574956 [patent_doc_number] => 10896883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Integrated circuit security [patent_app_type] => utility [patent_app_number] => 16/732724 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732724 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732724
Integrated circuit security Jan 1, 2020 Issued
Array ( [id] => 16744451 [patent_doc_number] => 10969431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Error-tolerant architecture for power-efficient computing [patent_app_type] => utility [patent_app_number] => 16/724576 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724576 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724576
Error-tolerant architecture for power-efficient computing Dec 22, 2019 Issued
Array ( [id] => 16758868 [patent_doc_number] => 10977420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Method of decomposing a layout for multiple-patterning lithography [patent_app_type] => utility [patent_app_number] => 16/724704 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724704 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724704
Method of decomposing a layout for multiple-patterning lithography Dec 22, 2019 Issued
Array ( [id] => 16096151 [patent_doc_number] => 20200202062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SYNCHRONOUS DEVICE WITH SLACK GUARD CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/723069 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723069
Synchronous device with slack guard circuit Dec 19, 2019 Issued
Array ( [id] => 16788297 [patent_doc_number] => 10990731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Dynamic voltage drop analysis with improved coverage [patent_app_type] => utility [patent_app_number] => 16/723870 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 15161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723870 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723870
Dynamic voltage drop analysis with improved coverage Dec 19, 2019 Issued
Array ( [id] => 17449085 [patent_doc_number] => 20220069590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => STANDBY POWER SUPPLY DEVICE AND METHOD FOR CHARGING SECONDARY BATTERY [patent_app_type] => utility [patent_app_number] => 17/417980 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17417980 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/417980
Standby power supply device and method for charging secondary battery Dec 18, 2019 Issued
Array ( [id] => 16501143 [patent_doc_number] => 10866524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Method and system for overlay control [patent_app_type] => utility [patent_app_number] => 16/719148 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719148
Method and system for overlay control Dec 17, 2019 Issued
Array ( [id] => 17430614 [patent_doc_number] => 20220058323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => COMPUTER-IMPLEMENTED METHOD FOR GENERATING A MIXED-LAYER FAULT TREE OF A MULTI-COMPONENT SYSTEM COMBINING DIFFERENT LAYERS OF ABSTRACTION [patent_app_type] => utility [patent_app_number] => 17/312459 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/312459
Computer-implemented method for generating a mixed-layer fault tree of a multi-component system combining different layers of abstraction Dec 16, 2019 Issued
Array ( [id] => 16637176 [patent_doc_number] => 10915687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Breadboard and electronics experimentation system [patent_app_type] => utility [patent_app_number] => 16/714404 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 11023 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714404
Breadboard and electronics experimentation system Dec 12, 2019 Issued
Array ( [id] => 16818271 [patent_doc_number] => 11003093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Process variability aware adaptive inspection and metrology [patent_app_type] => utility [patent_app_number] => 16/696263 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10342 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696263
Process variability aware adaptive inspection and metrology Nov 25, 2019 Issued
Array ( [id] => 15936695 [patent_doc_number] => 20200159981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => SYSTEMS AND METHODS FOR ASSEMBLING AND DEVELOPING AN SOC EFFICIENTLY USING TEMPLATES AND DESIGNER INPUT DATA [patent_app_type] => utility [patent_app_number] => 16/689031 [patent_app_country] => US [patent_app_date] => 2019-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 48661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689031 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689031
Systems and methods for assembling and developing an SoC efficiently using templates and designer input data Nov 18, 2019 Issued
Array ( [id] => 18087720 [patent_doc_number] => 11537857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Pooling processing method and system applied to convolutional neural network [patent_app_type] => utility [patent_app_number] => 16/678726 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8941 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678726
Pooling processing method and system applied to convolutional neural network Nov 7, 2019 Issued
Array ( [id] => 15904043 [patent_doc_number] => 20200151541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Efficient Convolutional Neural Networks [patent_app_type] => utility [patent_app_number] => 16/676757 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676757
Efficient convolutional neural networks Nov 6, 2019 Issued
Array ( [id] => 19949409 [patent_doc_number] => 12320769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Systems and methods for battery-less wirelessly powered dielectric sensors [patent_app_type] => utility [patent_app_number] => 17/287432 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 2341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287432
Systems and methods for battery-less wirelessly powered dielectric sensors Nov 3, 2019 Issued
Array ( [id] => 16431868 [patent_doc_number] => 10831954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs [patent_app_type] => utility [patent_app_number] => 16/667880 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667880
Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs Oct 28, 2019 Issued
Array ( [id] => 17319754 [patent_doc_number] => 20210408804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Cell Controller, Battery Controller, Battery Management System, and Battery System [patent_app_type] => utility [patent_app_number] => 17/294557 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17294557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/294557
Cell controller, battery controller, battery management system, and battery system Oct 8, 2019 Issued
Array ( [id] => 17288482 [patent_doc_number] => 11205032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Integrated circuit design method, system and computer program product [patent_app_type] => utility [patent_app_number] => 16/592200 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592200 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592200
Integrated circuit design method, system and computer program product Oct 2, 2019 Issued
Array ( [id] => 17535705 [patent_doc_number] => 20220114314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => VALIDATION PROCESSING DEVICE, VALIDATION PROCESSING METHOD, AND PROGRAM [patent_app_type] => utility [patent_app_number] => 17/278491 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17278491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/278491
Validation processing device, validation processing method, and program Oct 2, 2019 Issued
Array ( [id] => 16667523 [patent_doc_number] => 10936771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Using a common fuse controller hardware design for different applications [patent_app_type] => utility [patent_app_number] => 16/590977 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590977 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/590977
Using a common fuse controller hardware design for different applications Oct 1, 2019 Issued
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