Search

Phallaka Kik

Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2764, 2768, 2763, 2851, 2304
Total Applications
1951
Issued Applications
1745
Pending Applications
98
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19109051 [patent_doc_number] => 11962168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Wireless charging device [patent_app_type] => utility [patent_app_number] => 17/275718 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17275718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/275718
Wireless charging device Sep 29, 2019 Issued
Array ( [id] => 18911346 [patent_doc_number] => 11874323 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => JTAG-based burning device [patent_app_type] => utility [patent_app_number] => 17/615522 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17615522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/615522
JTAG-based burning device Sep 26, 2019 Issued
Array ( [id] => 15654605 [patent_doc_number] => 20200089833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => METHODS FOR ENGINEERING INTEGRATED CIRCUIT DESIGN AND DEVELOPMENT [patent_app_type] => utility [patent_app_number] => 16/583170 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 56196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583170
Methods for engineering integrated circuit design and development Sep 24, 2019 Issued
Array ( [id] => 16385499 [patent_doc_number] => 10810338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Method and device for generating boundary-scan interconnection lines [patent_app_type] => utility [patent_app_number] => 16/575890 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5763 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575890
Method and device for generating boundary-scan interconnection lines Sep 18, 2019 Issued
Array ( [id] => 16552097 [patent_doc_number] => 10885258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-05 [patent_title] => Fixing ESD path resistance errors in circuit design layout [patent_app_type] => utility [patent_app_number] => 16/576315 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576315 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576315
Fixing ESD path resistance errors in circuit design layout Sep 18, 2019 Issued
Array ( [id] => 16431876 [patent_doc_number] => 10831962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-10 [patent_title] => Resistor network generation from point-to-point resistance values [patent_app_type] => utility [patent_app_number] => 16/576617 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 7648 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576617 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576617
Resistor network generation from point-to-point resistance values Sep 18, 2019 Issued
Array ( [id] => 19311326 [patent_doc_number] => 12037126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-16 [patent_title] => Exergy/energy dynamics-based integrative modeling and control method for difficult electric aircraft missions [patent_app_type] => utility [patent_app_number] => 16/568904 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6004 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568904 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568904
Exergy/energy dynamics-based integrative modeling and control method for difficult electric aircraft missions Sep 11, 2019 Issued
Array ( [id] => 15982743 [patent_doc_number] => 10671700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Systems and methods for obfuscating a circuit design [patent_app_type] => utility [patent_app_number] => 16/564536 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 81 [patent_no_of_words] => 67098 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564536 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564536
Systems and methods for obfuscating a circuit design Sep 8, 2019 Issued
Array ( [id] => 15297945 [patent_doc_number] => 20190392108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/556831 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556831 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556831
Method and layout of an integrated circuit Aug 29, 2019 Issued
Array ( [id] => 16262887 [patent_doc_number] => 10754319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Across-wafer profile control in semiconductor processes [patent_app_type] => utility [patent_app_number] => 16/551038 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551038
Across-wafer profile control in semiconductor processes Aug 25, 2019 Issued
Array ( [id] => 16323347 [patent_doc_number] => 10783313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Method for improved cut metal patterning [patent_app_type] => utility [patent_app_number] => 16/549943 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549943 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549943
Method for improved cut metal patterning Aug 22, 2019 Issued
Array ( [id] => 17877722 [patent_doc_number] => 11449739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => General padding support for convolution on systolic arrays [patent_app_type] => utility [patent_app_number] => 16/548555 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8752 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548555 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548555
General padding support for convolution on systolic arrays Aug 21, 2019 Issued
Array ( [id] => 16463109 [patent_doc_number] => 10846458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Engineering change order cell structure having always-on transistor [patent_app_type] => utility [patent_app_number] => 16/546973 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 10046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546973
Engineering change order cell structure having always-on transistor Aug 20, 2019 Issued
Array ( [id] => 16209216 [patent_doc_number] => 20200242206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => APPARATUS AND METHOD OF OPERATING TIMING ANALYSIS CONSIDERING MULTI-INPUT SWITCHING [patent_app_type] => utility [patent_app_number] => 16/547497 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547497 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547497
Apparatus and method of operating timing analysis considering multi-input switching Aug 20, 2019 Issued
Array ( [id] => 16439313 [patent_doc_number] => 20200356639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => SIMULATION METHOD FOR USE IN FUNCTIONAL EQUIVALENCE CHECK [patent_app_type] => utility [patent_app_number] => 16/544928 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544928
Simulation method for use in functional equivalence check Aug 19, 2019 Issued
Array ( [id] => 16501702 [patent_doc_number] => 10867091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Machine learning based power optimization using parallel training and localized data generation [patent_app_type] => utility [patent_app_number] => 16/544092 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 11062 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544092
Machine learning based power optimization using parallel training and localized data generation Aug 18, 2019 Issued
Array ( [id] => 16574359 [patent_doc_number] => 10896283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-19 [patent_title] => Noise-based optimization for integrated circuit design [patent_app_type] => utility [patent_app_number] => 16/543070 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543070
Noise-based optimization for integrated circuit design Aug 15, 2019 Issued
Array ( [id] => 19720711 [patent_doc_number] => 12206258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Apparatus and method for providing charging status information in wireless power transmission system [patent_app_type] => utility [patent_app_number] => 17/432322 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 23040 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17432322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/432322
Apparatus and method for providing charging status information in wireless power transmission system Jul 29, 2019 Issued
Array ( [id] => 16617887 [patent_doc_number] => 20210036540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => POWER BACKUP ARCHITECTURE USING CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/525231 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525231 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525231
Power backup architecture using capacitor Jul 28, 2019 Issued
Array ( [id] => 19168345 [patent_doc_number] => 11984256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Wound component [patent_app_type] => utility [patent_app_number] => 17/264740 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2164 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17264740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/264740
Wound component Jul 25, 2019 Issued
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