
Phallaka Kik
Examiner (ID: 11978, Phone: (571)272-1895 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2764, 2768, 2763, 2851, 2304 |
| Total Applications | 1951 |
| Issued Applications | 1745 |
| Pending Applications | 98 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16958207
[patent_doc_number] => 11062078
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-07-13
[patent_title] => Insulation coordination method and system for a series compensation apparatus, storage medium and electronic device
[patent_app_type] => utility
[patent_app_number] => 16/493744
[patent_app_country] => US
[patent_app_date] => 2019-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6231
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493744
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/493744 | Insulation coordination method and system for a series compensation apparatus, storage medium and electronic device | Jul 24, 2019 | Issued |
Array
(
[id] => 16880225
[patent_doc_number] => 11030375
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Capturing routing intent by using a multi-level route pattern description language
[patent_app_type] => utility
[patent_app_number] => 16/522385
[patent_app_country] => US
[patent_app_date] => 2019-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 8645
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522385
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/522385 | Capturing routing intent by using a multi-level route pattern description language | Jul 24, 2019 | Issued |
Array
(
[id] => 16910637
[patent_doc_number] => 11042680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-22
[patent_title] => IC test information management system based on industrial internet
[patent_app_type] => utility
[patent_app_number] => 16/521926
[patent_app_country] => US
[patent_app_date] => 2019-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 14724
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 237
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521926
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/521926 | IC test information management system based on industrial internet | Jul 24, 2019 | Issued |
Array
(
[id] => 17352445
[patent_doc_number] => 11227084
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-18
[patent_title] => Multi-bit standard cell
[patent_app_type] => utility
[patent_app_number] => 16/522586
[patent_app_country] => US
[patent_app_date] => 2019-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522586
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/522586 | Multi-bit standard cell | Jul 24, 2019 | Issued |
Array
(
[id] => 15903537
[patent_doc_number] => 20200151288
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-14
[patent_title] => Deep Learning Testability Analysis with Graph Convolutional Networks
[patent_app_type] => utility
[patent_app_number] => 16/520688
[patent_app_country] => US
[patent_app_date] => 2019-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520688
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/520688 | Deep learning testability analysis with graph convolutional networks | Jul 23, 2019 | Issued |
Array
(
[id] => 15116087
[patent_doc_number] => 20190344676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-14
[patent_title] => MECHANISM FOR LOCKING AND FAULT DETECTION IN AN ELECTRICAL VEHICLE SUPPLY EQUIPMENT CORD REEL
[patent_app_type] => utility
[patent_app_number] => 16/519882
[patent_app_country] => US
[patent_app_date] => 2019-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2773
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519882
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/519882 | Mechanism for locking and fault detection in an electrical vehicle supply equipment cord reel | Jul 22, 2019 | Issued |
Array
(
[id] => 16863911
[patent_doc_number] => 11022649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Stabilised failure estimate in circuits
[patent_app_type] => utility
[patent_app_number] => 16/512911
[patent_app_country] => US
[patent_app_date] => 2019-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 11565
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512911
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/512911 | Stabilised failure estimate in circuits | Jul 15, 2019 | Issued |
Array
(
[id] => 16193085
[patent_doc_number] => 20200233934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-23
[patent_title] => COMPUTER-IMPLEMENTED METHOD, PROCESSOR-IMPLEMENTED SYSTEM, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING INSTRUCTIONS FOR SIMULATION OF PRINTED CIRCUIT BOARD
[patent_app_type] => utility
[patent_app_number] => 16/507834
[patent_app_country] => US
[patent_app_date] => 2019-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7216
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507834
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/507834 | Computer-implemented method, processor-implemented system, and non-transitory computer-readable storage medium storing instructions for simulation of printed circuit board | Jul 9, 2019 | Issued |
Array
(
[id] => 16592904
[patent_doc_number] => 10902171
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-01-26
[patent_title] => Clock crossing interface for integrated circuit generation
[patent_app_type] => utility
[patent_app_number] => 16/506507
[patent_app_country] => US
[patent_app_date] => 2019-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12566
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16506507
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/506507 | Clock crossing interface for integrated circuit generation | Jul 8, 2019 | Issued |
Array
(
[id] => 16494734
[patent_doc_number] => 10860777
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Method and system for fabricating integrated circuit with aid of programmable circuit synthesis
[patent_app_type] => utility
[patent_app_number] => 16/443055
[patent_app_country] => US
[patent_app_date] => 2019-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8385
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443055
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/443055 | Method and system for fabricating integrated circuit with aid of programmable circuit synthesis | Jun 16, 2019 | Issued |
Array
(
[id] => 14935773
[patent_doc_number] => 20190303524
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => ELEMENT REMOVAL DESIGN IN MICROWAVE FILTERS
[patent_app_type] => utility
[patent_app_number] => 16/443466
[patent_app_country] => US
[patent_app_date] => 2019-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6324
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16443466
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/443466 | Element removal design in microwave filters | Jun 16, 2019 | Issued |
Array
(
[id] => 16478593
[patent_doc_number] => 10853542
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-01
[patent_title] => Fuse-based logic repair
[patent_app_type] => utility
[patent_app_number] => 16/442347
[patent_app_country] => US
[patent_app_date] => 2019-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 8728
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442347
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/442347 | Fuse-based logic repair | Jun 13, 2019 | Issued |
Array
(
[id] => 18997162
[patent_doc_number] => 11913998
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Management device and power supply system
[patent_app_type] => utility
[patent_app_number] => 17/261101
[patent_app_country] => US
[patent_app_date] => 2019-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 7048
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261101
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/261101 | Management device and power supply system | Jun 11, 2019 | Issued |
Array
(
[id] => 15258211
[patent_doc_number] => 20190377839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => EFFICIENT BI-DIRECTIONAL PROPERTY-BASED PATH TRACING
[patent_app_type] => utility
[patent_app_number] => 16/432396
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10263
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432396
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/432396 | Efficient bi-directional property-based path tracing | Jun 4, 2019 | Issued |
Array
(
[id] => 16494718
[patent_doc_number] => 10860761
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-12-08
[patent_title] => Systems and methods for enhanced clock tree power estimation at register transfer level
[patent_app_type] => utility
[patent_app_number] => 16/430584
[patent_app_country] => US
[patent_app_date] => 2019-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 5160
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430584
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/430584 | Systems and methods for enhanced clock tree power estimation at register transfer level | Jun 3, 2019 | Issued |
Array
(
[id] => 15715383
[patent_doc_number] => 20200104458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 16/429592
[patent_app_country] => US
[patent_app_date] => 2019-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13111
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429592
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/429592 | Static voltage drop (SIR) violation prediction systems and methods | Jun 2, 2019 | Issued |
Array
(
[id] => 14840947
[patent_doc_number] => 20190278874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-12
[patent_title] => INTEGRATED CIRCUIT BUFFERING SOLUTIONS CONSIDERING SINK DELAYS
[patent_app_type] => utility
[patent_app_number] => 16/423391
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7675
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423391
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/423391 | Integrated circuit buffering solutions considering sink delays | May 27, 2019 | Issued |
Array
(
[id] => 15232233
[patent_doc_number] => 10503841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-10
[patent_title] => Integrated circuit buffering solutions considering sink delays
[patent_app_type] => utility
[patent_app_number] => 16/423242
[patent_app_country] => US
[patent_app_date] => 2019-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7673
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423242
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/423242 | Integrated circuit buffering solutions considering sink delays | May 27, 2019 | Issued |
Array
(
[id] => 16911654
[patent_doc_number] => 11043705
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-06-22
[patent_title] => Cell having implanted electronic circuit
[patent_app_type] => utility
[patent_app_number] => 16/421626
[patent_app_country] => US
[patent_app_date] => 2019-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4613
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421626
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/421626 | Cell having implanted electronic circuit | May 23, 2019 | Issued |
Array
(
[id] => 14782811
[patent_doc_number] => 20190266303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => FALSE PATH TIMING EXCEPTION HANDLER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/410391
[patent_app_country] => US
[patent_app_date] => 2019-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410391
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/410391 | False path timing exception handler circuit | May 12, 2019 | Issued |