Phallaka Kik

Array ( [id] => 18599260 [patent_doc_number] => 20230274060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => AUTOMATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 18/314038 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19228659 [patent_doc_number] => 12008296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Automated circuit generation [patent_app_type] => utility [patent_app_number] => 18/314000 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 110 [patent_no_of_words] => 64608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18599258 [patent_doc_number] => 20230274058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => AUTOMATED CIRCUIT GENERATION [patent_app_type] => utility [patent_app_number] => 18/314012 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 64614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19443350 [patent_doc_number] => 12093618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Automated circuit generation [patent_app_type] => utility [patent_app_number] => 18/314007 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 110 [patent_no_of_words] => 64666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19228659 [patent_doc_number] => 12008296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Automated circuit generation [patent_app_type] => utility [patent_app_number] => 18/314000 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 110 [patent_no_of_words] => 64608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19293542 [patent_doc_number] => 12032896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Generation of layout including power delivery network [patent_app_type] => utility [patent_app_number] => 18/312835 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 11459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18487229 [patent_doc_number] => 20230214575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/183056 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19434906 [patent_doc_number] => 20240303404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => USING MACHINE VISION TO SOLVE INDUSTRIAL BOOLEAN SATISFIABILITY (SAT) PROBLEMS [patent_app_type] => utility [patent_app_number] => 18/181200 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19434906 [patent_doc_number] => 20240303404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => USING MACHINE VISION TO SOLVE INDUSTRIAL BOOLEAN SATISFIABILITY (SAT) PROBLEMS [patent_app_type] => utility [patent_app_number] => 18/181200 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18471680 [patent_doc_number] => 20230205966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION LAYER [patent_app_type] => utility [patent_app_number] => 18/173731 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19391711 [patent_doc_number] => 20240281581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => LIBRARY SCALING FOR CIRCUIT DESIGN ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/111263 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19006290 [patent_doc_number] => 20240070361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CIRCUIT ANALYSIS METHOD, CIRCUIT ANALYSIS DEVICE, AND CIRCUIT ANALYSIS SYSTEM [patent_app_type] => utility [patent_app_number] => 18/166055 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925802 [patent_doc_number] => 20240028806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METHOD OF DESIGNING TERNARY LOGIC CIRCUIT USING MOSFETS HAVING DEPLETION-MODE AND MULTI-VTHS, AND DEVICE AND RECORDING MEDIUM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/096344 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925802 [patent_doc_number] => 20240028806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METHOD OF DESIGNING TERNARY LOGIC CIRCUIT USING MOSFETS HAVING DEPLETION-MODE AND MULTI-VTHS, AND DEVICE AND RECORDING MEDIUM FOR PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/096344 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303905 [patent_doc_number] => 20240232485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => TEST POINT INSERTION IN ANALOG CIRCUIT DESIGN TESTING [patent_app_type] => utility [patent_app_number] => 18/094951 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303905 [patent_doc_number] => 20240232485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => TEST POINT INSERTION IN ANALOG CIRCUIT DESIGN TESTING [patent_app_type] => utility [patent_app_number] => 18/094951 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303906 [patent_doc_number] => 20240232486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => USING SURROGATE NETLISTS FOR VARIATION ANALYSIS OF PROCESS VARIATIONS [patent_app_type] => utility [patent_app_number] => 18/152069 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19284214 [patent_doc_number] => 20240220690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Synthesis and Verification of an Integrated Circuit (IC) [patent_app_type] => utility [patent_app_number] => 18/091755 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18668814 [patent_doc_number] => 11775718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Methods and apparatus to simulate metastability for circuit design verification [patent_app_type] => utility [patent_app_number] => 18/072842 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 13993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18072842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881706 [patent_doc_number] => 20240005075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => GRAPHIC NEURAL NETWORK ACCELERATION SOLUTION WITH CUSTOMIZED BOARD FOR SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 18/071970 [patent_app_country] => US [patent_app_date] => 2022-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071970 [rel_patent_id] =>[rel_patent_doc_number] =>)